usb_new_rcv_ram_ent.vhdl

实现USB接口功能的VHDL和verilog完整源代码

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--
--  P H I L I P S  C O M P A N Y  R E S T R I C T E D
--                                         
--  Copyright (c) 1998.                    
--                                           
--  Philips Electronics N.V.                   
--                                           
--  Philips Semiconductors                 
--  Interconnectivity and Processor Peripheral group
--  Bangalore,India                           
--  All rights reserved. Reproduction in whole or in part is prohibited
--  without the written permission of the copyright owner.
--
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--  File            : usb_new_rcv_ram_ent.vhdl 
--
--  Module          : Receive RAM Manager
--
--  Project         : VPB bus interface to USB 1.1 device (USBFS22)
--
--  Author          :             
--
--  Description     : The entity of receive RAM manager block 
--
--  Contact address : [e-mail]
--
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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

library work;
use work.PCK_CONFIGURATION.all;
use work.PCK_GENERAL.all;
use work.PCK_HANDLERS.all;

library work;
use work.PCK_APB.all; 

entity RCV_RAM  is
     port(  
          -- Interface to SYNCHRONIZER module

          If_Busy:             in    boolean;               -- Data available in rcv_transmt.
          RxCore_Data:         in    byte;                  -- The Data to be transferred.
          EP_number_out:       in    Int_EndPointType;      -- Physical endpoint number
          Rx_N_data:           in    integer range 0 to MAX_OVERFLOW_SIZE; -- Packet size
          End_Transfer_D:      in    one_bit;               -- End of transfer for packet data
          RxError_Out:         in    boolean;               -- Error in data packet transfer
          FullBuffer_EP:       in    T_Full;                -- Full buffer for endpoints
          USBToggleBuffer_Out: in    T_ToggleArray;         -- USB toggle buffer
          UCToggleBuffer_Out:  in    T_ToggleArray;         -- UC Toggle buffer
          PI_IsoToggle_Out:    in    integer range 0 to 1;  -- ISO toggle buffer
          RxDataAccepted:      out   boolean;               -- Data accepted
          
          -- Interface to RAM module

          RxRAM_DQ_In:         in    four_bytes;            -- RAM data in-bus (32-bits)
          RxRAM_E_N:           out   one_bit;               -- RAM enable, active low
          RxRAM_W_N:           out   one_bit;               -- RAM write, active low
          RxRAM_G_N:           out   one_bit;               -- RAM grant(read), active low
          RxRAM_A:             out   RxRAMAddr_bits;        -- RAM address bus (??-bits)
          RxRAM_DQ_Out:        out   four_bytes;            -- RAM data out-bus(32-bits)

          -- Interface to USB_CONTROLLER module
          DataFromRam:         out   four_bytes;            -- Data read from RAM
          RxRam_Read:          in    one_bit;               -- RAM read
          Rx_Pkt_End:          in    one_bit;               -- End of packet read
          Endpoint_Nr:         in    logical_ep_type;       -- Logical endpoint
          write_pkt_length:    out   boolean;               -- Write packet length
          
          -- Clock and reset from system

          clk:                 in    one_bit;               -- APB bus clock
          pvci_reset_n:        in    one_bit                -- APB bus Reset
        );
end  RCV_RAM ;