📄 usb_new_vsc9_ram_cm0.vhd
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-- HDLi Version 5.0 IP Bundle 2000.12.15
-- Top HDL file name is usb_new.vhd
-- -----------------------------------------------------------------------------
-- Royal Philips Electronics
-- -----------------------------------------------------------------------------
-- Copyright 2001 by Royal Philips Electronics All rights reserved.
--
-- This module is property of Royal Philips Electronics (Philips) and its use
-- is granted to the customer for the sole purpose of implementing in silicon
-- provided by Philips. This module may only be used in accordance with the
-- provisions of the HDLi License Agreement.
--
-- -----------------------------------------------------------------------------
-- USBFS22 Device Version 1.0
-- -----------------------------------------------------------------------------
-- usb_new/data/USBFS22/RTL/usb_new_vsc9_ram_cm0.vhd : RTL VHDL
--
-- Compiled by arkrish on Tue Apr 3 17:23:42 2001
-- -----------------------------------------------------------------------------
-- HDLi Version 5.0 IP Bundle 2000.12.15
-- Top HDL file name is vsc9_ram.vhd
-- -----------------------------------------------------------------------------
-- Royal Philips Electronics
-- -----------------------------------------------------------------------------
-- Copyright 2001 by Royal Philips Electronics All rights reserved.
--
-- This module is property of Royal Philips Electronics (Philips) and its use
-- is granted to the customer for the sole purpose of implementing in silicon
-- provided by Philips. This module may only be used in accordance with the
-- provisions of the HDLi License Agreement.
--
-- -----------------------------------------------------------------------------
-- BIST SRAM Template Version 2.4
-- -----------------------------------------------------------------------------
-- vsc9_ram_cm0.vhd : RTL VHDL
--
-- Compiled by arkrish on Tue Apr 3 11:53:35 2001
-- -----------------------------------------------------------------------------
-- -----------------------------------------------------------------------------
-- Functional Description:
--
-- This is a sample block that includes a BIST client, the associated
-- memory and the related MUX logic. The block references
-- the following modules:
-- top level ____ BIST client
-- |__ BIST RAM
-- -----------------------------------------------------------------------------
-- Limitations: None known at this time.
-- -----------------------------------------------------------------------------
-- Critical Timing:
-- -----------------------------------------------------------------------------
-- Non-Portable Instantiations:
-- -----------------------------------------------------------------------------
-- Targeted Technologies: vsc883
-- -----------------------------------------------------------------------------
-- Author: System Technology Creation Date: October, 1997
-- -----------------------------------------------------------------------------
-- Revision History:
-- 1.0 10/97 Initial Release
-- -----------------------------------------------------------------------------
-- -----------------------------------------------------------------------------
-- Client BIST with Instantiated Memory
-- -----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
----use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
----use WORK.vsc9_ram_c0_pkg.ALL; -- Client package
----use WORK.vsc9_ram_xor_pkg.ALL; -- XOR package
library work;
use work.vsc9_ram_xor_pkg.all;
use work.all;
entity vsc9_ram_cm0 is
port ( sys_ck0 : in STD_LOGIC; -- System Memory Address Strobe
sys_en0 : in STD_LOGIC; -- System Memory Block Select
sys_we0 : in STD_LOGIC; -- System Memory Write Enable
sys_ad0 : in STD_LOGIC_VECTOR(6 downto 0); -- System Memory Address Bus
sys_di0 : in STD_LOGIC_VECTOR(31 downto 0); -- System Memory Data Input
sys_do0 : out STD_LOGIC_VECTOR(31 downto 0); -- System Memory Data Output
scantestmode : in STD_LOGIC; -- Scan Test Mode
scanclock : in STD_LOGIC; -- Scan Clock
tck : in STD_LOGIC; -- Test Clock
chb : in STD_LOGIC_VECTOR(15 downto 0); -- Client Host Bus
tdi : in STD_LOGIC; -- Test Data Input
tdo : out STD_LOGIC); -- Test Data Output
end vsc9_ram_cm0;
architecture RTL of vsc9_ram_cm0 is
component spram96x32
port (
as : in std_logic; -- RAM address strobe
di : in std_logic_vector(31 downto 0); -- RAM data in
dout: out std_logic_vector(31 downto 0); -- RAM data out
bs : in std_logic; -- RAM block enable
we : in std_logic; -- RAM write enable
a : in std_logic_vector(6 downto 0)); -- RAM address
end component;
component vsc9_ram_c0
port ( tck : in STD_LOGIC;
chb : in STD_LOGIC_VECTOR(15 downto 0);
tdi : in STD_LOGIC;
dout : in STD_LOGIC_VECTOR(31 downto 0);
di : out STD_LOGIC_VECTOR(31 downto 0);
a : out STD_LOGIC_VECTOR(6 downto 0);
bs : out STD_LOGIC;
we : out STD_LOGIC;
tdo : out STD_LOGIC;
tbe : out STD_LOGIC);
end component;
-- for internal signals
signal t_tbe: std_logic;
signal ck0: std_logic;
signal ad0: std_logic_vector(6 downto 0);
signal en0: std_logic;
signal we0: std_logic;
signal di0: std_logic_vector(31 downto 0);
signal do0_ram: std_logic_vector(31 downto 0);
signal do0_client: std_logic_vector(31 downto 0);
signal t_ad0: std_logic_vector(6 downto 0);
signal t_di0: std_logic_vector(31 downto 0);
signal t_en0: std_logic;
signal t_we0: std_logic;
signal xorbus: STD_LOGIC_VECTOR(3 downto 0);
signal scantestbit: STD_LOGIC;
begin
v_client0: vsc9_ram_c0
port map (tck => tck, -- test clock
chb => chb, -- client host bus
tdi => tdi, -- test data input
dout => do0_client, -- memory data output
we => t_we0, -- memory write enable
bs => t_en0, -- memory block select
di => t_di0, -- memory data input
a => t_ad0, -- memory address bus
tdo => tdo, -- test data output
tbe => t_tbe); -- test BIST enable
v_memory0: spram96x32
port map (
as => ck0, -- RAM address strobe
di => di0, -- RAM data in
bs => en0, -- RAM block select
we => we0, -- RAM write enable
a => ad0, -- RAM address
dout => do0_ram); -- RAM data out
ck0 <= tck WHEN t_tbe='1' ELSE sys_ck0;
di0 <= t_di0 WHEN t_tbe='1' ELSE sys_di0;
en0 <= t_en0 WHEN t_tbe='1' ELSE sys_en0;
we0 <= t_we0 WHEN t_tbe='1' ELSE sys_we0;
ad0 <= t_ad0 WHEN t_tbe='1' ELSE sys_ad0;
do0_client <= (others => scantestbit) WHEN scantestmode = '1' ELSE do0_ram;
sys_do0 <= do0_client;
-- Scan mode bypass logic to test all the faults between the memory
-- and the BIST. scantestbit should be added to the scan chain.
xorbus(0) <= vsc9_ram_reduce_xor(di0);
xorbus(1) <= vsc9_ram_reduce_xor(ad0);
xorbus(2) <= en0;
xorbus(3) <= we0;
scantest_register: process (scanclock)
begin
if (scanclock = '1' and scanclock'event) then
if (scantestmode = '1') then
scantestbit <= vsc9_ram_reduce_xor(xorbus);
end if;
end if;
end process;
end RTL; --vsc9_ram_cm0.vhd
-- -----------------------------------------------------------------------------
-- VHDL Component Instantiation:
-- -----------------------------------------------------------------------------
-- component vsc9_ram_cm0
-- port ( sys_ck0 : in STD_LOGIC;
-- sys_en0 : in STD_LOGIC;
-- sys_we0 : in STD_LOGIC;
-- sys_ad0 : in STD_LOGIC_VECTOR(6 downto 0);
-- sys_di0 : in STD_LOGIC_VECTOR(31 downto 0);
-- sys_do0 : out STD_LOGIC_VECTOR(31 downto 0);
-- scantestmode : in STD_LOGIC;
-- scanclock : in STD_LOGIC;
-- tck : in STD_LOGIC;
-- chb : in STD_LOGIC_VECTOR(15 downto 0);
-- tdi : in STD_LOGIC;
-- tdo : out STD_LOGIC);
-- end component;
--
-- u1: vsc9_ram_cm0
-- port map ( sys_ck0 => , -- System Memory Address Strobe
-- sys_en0 => , -- System Memory Block Select
-- sys_we0 => , -- System Memory Write Enable
-- sys_ad0 => , -- System Memory Address Bus
-- sys_di0 => , -- System Memory Data Input
-- sys_do0 => , -- System Memory Data Output
-- scantestmode => , -- Scan Test Mode
-- scanclock => , -- Scan Clock
-- tck => , -- Test Clock
-- chb => , -- Client Host Bus
-- tdi => , -- Test Data Input
-- tdo => ); -- Test Data Output
-- -----------------------------------------------------------------------------
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