usb_new_glue_rtl.vhdl

实现USB接口功能的VHDL和verilog完整源代码

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--
--  P H I L I P S  C O M P A N Y  R E S T R I C T E D
--                                         
--  Copyright (c) 1998.                    
--
--  Philips Electronics N.V.
--
--  Philips Semiconductors
--  Interconnectivity and Processor Peripheral group
--  Bangalore,India
--  All rights reserved. Reproduction in whole or in part is prohibited
--  without the written permission of the copyright owner.
--
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--
--  File            : usb_new_glue_rtl.vhdl 
--
--  Module          : GLUE 
--
--  Project         : VPB bus Interface to USB 1.1 Device(USBFS22)
--
--  Author          :              
--
--  Description     :The architecture of GLUE module. This module does the 
--                   conversion of unsigned to std_logic & vice versa.
--
--  Status          : 
--
--  Contact address : 
--
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library ieee;
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;

library work;
use work.PCK_GENERAL.all;
use work.PCK_USB.all;
use work.PCK_CONFIGURATION.all;
use work.PCK_SETUP.all;

library work;
use work.PCK_APB.all;

architecture RTL of GLUE is
begin
           -- pvci interface signals
           r_data               <= std_logic_vector(USB_r_data);                    
           gnt                  <= USB_gnt;                
           USB_clk              <= clk;
           USB_reset_n          <= USB_AsynReset_N;
	   pvci_reset_n_out     <= pvci_reset_n;
           USB_req              <= req;
           USB_address          <= unsigned(address);
           USB_rnw              <= rnw;
           USB_w_data           <= unsigned(w_data);
           USB_Int_Req_Irq      <= Intr_Request_Irq;
           USB_Int_Req_Fiq      <= Intr_Request_Fiq;
           
           ---------- Clocks ---------
           Clk12MHzRef          <= LOW;
           Clk48MHz             <= USB_MainClk;
           USB_NeedClk          <= TM_ClockOn;
       
           FsClk                <= USB_BitClk;
           HB_UsbLineBits(0)    <= USB_UP_RxDM;
           HB_UsbLineBits(1)    <= USB_UP_RxDP;
           HB_UsbDifBit         <= USB_UP_RxRCV;

           HC_ResetDevice       <= (others => FALSE);
           USB_BitClk_Out       <= Clk12MHz_O;
       
           ---------- Connect ---------
           USB_Connect_N        <= conv_active_low(DH_Connect);
       
           ---------- Misc ---------
           ChipID               <= ("0010000000000000");
           PINConfigArray       <= (others => FALSE);    ---- ????
           Suspend_In           <= TRUE;
           TestMode             <= USB_TestMode;
           VBusAvailable        <= conv_active_high(USB_VBus);
                          
           ---------- Raminterface ---------
           RxRAM_DQ_In          <= unsigned(USB_RxRAM_DQ_In);
           TxRAM_DQ_In          <= unsigned(USB_TxRAM_DQ_In);

           USB_RxRAM_E_N        <= RxRAM_E_N;
           USB_RxRAM_W_N        <= RxRAM_W_N;
           USB_RxRAM_G_N        <= RxRAM_G_N;
           USB_RxRAM_A          <= std_logic_vector(RxRAM_A);
           USB_RxRAM_DQ_Out     <= std_logic_vector(RxRAM_DQ_Out);	     

           USB_TxRAM_E_N        <= TxRAM_E_N;
           USB_TxRAM_W_N        <= TxRAM_W_N;
           USB_TxRAM_G_N        <= TxRAM_G_N;
           USB_TxRAM_A          <= std_logic_vector(TxRAM_A);
           USB_TxRAM_DQ_Out     <= std_logic_vector(TxRAM_DQ_Out);
           
           ---------- Suspend ---------
           USB_Suspend          <= USB_Suspended;       
        
           ---------- General ---------
           RemoteWakeup         <= FALSE;
        
           ---------- Upstream port ---------
           UP_DsLineBits(0)     <= USB_UP_RxDM;            
           UP_DsLineBits(1)     <= USB_UP_RxDP;            
           USB_UP_LED_N         <= not(Configured_LED);
           USB_UP_TxDM          <= UP_DM;
           USB_UP_TxDP          <= UP_DP;             
           USB_UP_TxEnable_N    <= SIE_UsbEnable_N;

end RTL;