usb_new_ep_handler_ent.vhdl

实现USB接口功能的VHDL和verilog完整源代码

--------------------------------------------------------------------------------
--
--  P H I L I P S  C O M P A N Y  R E S T R I C T E D
--                                         
--  Copyright (c) 1998.                    
--
--  Philips Electronics N.V.
--
--  Philips Semiconductors
--  Interconnectivity and Processor Peripheral group
--  Bangalore, India
--  All rights reserved. Reproduction in whole or in part is prohibited
--  without the written permission of the copyright owner.
--
--------------------------------------------------------------------------------
--
--  File            :  usb_new_ep_handler_ent.vhdl 
--
--  Module          :  EP_HANDLER
--
--  Project         :  VPB bus interface to USB 1.1 device (USBFS22)
--
--  Author          :              
--
--  Description     : The entity of EP handler 
--
--  Contact address : [e-mail]
--
--------------------------------------------------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

LIBRARY work;
use work.PCK_GENERAL.all;
use work.PCK_HANDLERS.all;
use work.PCK_CONFIGURATION.all;

LIBRARY work;
use work.PCK_APB.all;

entity EP_HANDLER is
     port ( 
           -- Interface to SYNCHRONIZER module

           If_Busy:            in   boolean;              -- Interface busy
           Data_In:            in   byte;                 -- IN Data to PI handler                
           CommandCodeChannel: in   eleven_bits;          -- Command code
           CmdCodeValid_Out:   in   boolean;              -- Command code valid
           Trans_Enable:      out   one_bit;              -- Transfer to Interface enabled
           Read:              out   one_bit;              -- Read from Interface
           Data_Out:          out   byte;                 -- Data from PI handler.
           EP_number:         out   Int_EndPointType;     -- Physical endpoint
           End_Transfer:      out   one_bit;              -- End of packet data 
           EndTransfer_Cmd:   out   one_bit;              -- End of command data
           Rx_N_data:         out   integer range 0 to MAX_OVERFLOW_SIZE; -- Size of OUT packet
           USBEp0Intr_Set:    out   one_bit;              -- USB Ep0 interrupt
           USBEp1Intr_Set:    out   one_bit;              -- USB Ep1 interrupt
           USBEp2Intr_Set:    out   one_bit;              -- USB Ep2 interrupt
           USBEp3Intr_Set:    out   one_bit;              -- USB Ep3 interrupt
           USBEp4Intr_Set:    out   one_bit;              -- USB Ep4 interrupt
           USBEp5Intr_Set:    out   one_bit;              -- USB Ep5 interrupt
           USBEp6Intr_Set:    out   one_bit;              -- USB Ep6 interrupt
           USBEp7Intr_Set:    out   one_bit;              -- USB Ep7 interrupt
           USBDevIntr_Set:    out   one_bit;              -- USB Dev interrupt
           
           USBToggleBuffer:   out   T_ToggleArray;        -- USB toggle buffer
           UCToggleBuffer:    out   T_ToggleArray;        -- UC toggle buffer
           RxError:           out   boolean;              -- Error in packet transfer
           FullBuffer_UC:     out   T_Full;               -- Full buffer 
           PI_IsoToggle:      out   integer range 0 to 1; -- ISO toggle buffer
           CommandData:       out   byte;                 -- Command data
           CmdAccept:         out   boolean;              -- Command accepted
           CmdDataValid:      out   boolean;              -- Command data valid
           reg_ram_read:      out   one_bit;              -- Start of IN transfer
           reg_ram_tag:       out   Int_EndPointType;     -- Physical endpoint number

           -- Interface to TRNSMT_RAM module
           Read_Req:           in   one_bit;              -- Data available in GIF.   
           TxDest_NData:       in   nine_bits;            -- Number of bytes for IN packet

           -- Interface to UC_HANDLER module

           DataToUC_In:        in    T_Handlers_to_UC;    -- Command data record 
           Uc_To_Pi:           in    T_UC_to_pi_handler;  -- Data record
           Sie_Write:          in    one_bit;             -- Write into EP_HANDLER
           Sie_Read:           in    one_bit;             -- Read from EP_HANDLER
           SIE_EndTransfer:    in    one_bit;             -- End of transfer
           RxError_SIE:        in    boolean;             -- Error
           Start_In_Transfer:  in    one_bit;             -- Start of IN transfer
           SIE_N_Data:         in    integer range 0 to MAX_OVERFLOW_SIZE;
           EPBufferInfo:       in    T_EPBufferInfo;
           N_Data_EP:         out    nine_bits;
           Pi_To_Uc:          out    T_pi_to_uc_handler;
           DataFromUC:        out    T_UC_to_Handlers;
           DataToUC_Out:      out    T_Handlers_to_UC;
           
           -- Interface to DEVICE_HANDLER module

           DH_Interrupt_Ep0:   in    boolean;
           DH_Interrupt_Ep1:   in    boolean;
           DH_Interrupt_Ep2:   in    boolean;
           DH_Interrupt_Ep3:   in    boolean;
           DH_Interrupt_Ep4:   in    boolean;
           DH_Interrupt_Ep5:   in    boolean;
           DH_Interrupt_Ep6:   in    boolean;
           DH_Interrupt_Ep7:   in    boolean;
           DH_Interrupt_Dev:   in    boolean;
           
           -- Interface to TIMERS_SF module

           TM_IsoToggle:       in    integer range 0 to 1;

           -- clock and reset from system     

           FsClk:             in     one_bit;
           Reset_N:           in     std_logic
          );           
END EP_HANDLER;