usb_new_vpb_wrapper_ent.vhdl

实现USB接口功能的VHDL和verilog完整源代码

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 -- P H I L I P S  C O M P A N Y  R E S T R I C T E D
 --                                         
 --  Copyright (c) 1998.                    
 --
 --  Philips Electronics N.V.
 --
 --  Philips Semiconductors
 --  Interconnectivity and Processor Peripherals group
 --  Bangalore,India
 --  All rights reserved. Reproduction in whole or in part is prohibited
 --  without the written permission of the copyright owner.
 --
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 --
 --
 --  File            : usb_new_vpb_wrapper_ent.vhdl 
 --
 --  Module          : VPB_WRAPPER
 --
 --  Project         : VPB bus interface to USB1.1 device (USBFS22)
 --
 --  Author          :              
 --
 --  Description     : The entity of  VPB WRAPPER module
 --
 --  Contact address : [e-mail]
 --
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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity VPB_WRAPPER is
   port(
         -- Interface to VPB bus

         PSEL:          in      std_logic;                      -- Peripheral select
         PENABLE:       in      std_logic;                      -- Peripheral enable
         PADDR:         in      std_logic_vector(7 downto 0);   -- Peripheral address
         PWRITE:        in      std_logic;                      -- '1' write, '0' read
         PRESETn:       in      std_logic;                      -- Reset
         PCLK:          in      std_logic;                      -- CLock
         PWDATA:        in      std_logic_vector(31 downto 0);  -- Write data
         PRDATA:        out     std_logic_vector(31 downto 0);  -- Read data
         PRDY:          out     std_logic;                      -- Wait state
         
       
         -- Interface to PVCI_CNTRL module

         r_data:        in      std_logic_vector(31 downto 0);  -- read data
         gnt:           in      std_logic;                      -- Grant
         pvci_reset_n:  out     std_logic;                      -- PVCI reset
         req:           out     std_logic;                      -- Request
         address:       out     std_logic_vector(7 downto 0);   -- Address
         rnw:           out     std_logic;                      -- '0' write, '1' read
         w_data:        out     std_logic_vector(31 downto 0);  -- PVCI write data
         error:         in      std_logic
          
         );
 end VPB_WRAPPER;