usb_new_rcv_ram_rtl.vhdl

实现USB接口功能的VHDL和verilog完整源代码

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--
--  P H I L I P S  C O M P A N Y  R E S T R I C T E D
--                                         
--  Copyright (c) 1998.                    
--
--  Philips Electronics N.V.
--
--  Philips Semiconductors
--  Interconnectivity and Processor Peripheral group
--  Bangalore,India
--  All rights reserved. Reproduction in whole or in part is prohibited
--  without the written permission of the copyright owner.
--------------------------------------------------------------------------------
--
--  File            : usb_new_rcv_ram_rtl.vhdl 
--
--  Module          : Recieve RAM manager
--
--  Project         : VPB bus interface to USB 1.1 device (USBFS22)
--
--  Author          :              
--
--  Description     : The Architecture of RAM manager module. This module handles 
--                    writing of USB data into the RAM and reading of data from
--                    RAM by processor side.
--                    PROCEDURE for writing the data:
--                    1. Get the buffer number in RAM for an endpoint
--                    2. Get the start address of the buffer
--                    3. Leave one address in the buffer for header
--                    4. Write the data
--                    5. Update the header
--                    PROCEDURE for reading the data:
--                    1. Get the buffer number in RAM for an endpoint
--                    2. Get the start address of the buffer
--                    3. Read the header which holds packet_length and valid bit
--                    4. Read the data
--                    For ISO endpoints, each buffer has a Full flag to indicate if
--                    there was a data in the previous frame, otherwise send an
--                    empty packet to the processor on request
--                    Whenever Rx_Pkt_End comes, reset RxRdAdPointer
--
--  Contact address : [e-mail]
--
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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

library work ;
use work.PCK_GENERAL.all;

library work;
use work.PCK_APB.all; 

architecture RTL of RCV_RAM is
  
  signal  RxDataAccepted_I:     boolean;                      -- Data accepted        
  signal  RxDataCount:          Int_CountDatatype;            -- Counter 
  signal  RAMAddress_Wr:        RxRAMAddr_bits;               -- RAM write address
  signal  RAMAddress_Rd:        RxRAMAddr_bits;               -- RAM write address
  signal  RAMAddress:           RxRAMAddr_bits;               -- RAM address
  signal  RAM_WriteReq:         boolean;                      -- RAM wirite request
  signal  write:                one_bit;                      -- RAM write
  signal  RAMData:              four_bytes;                   -- RAM write data
  signal  RAM_WriteGrant:       boolean;                      -- RAM write grant
  signal  ByteCount:            Int_ThreeBits;                -- Byte counter
  signal  MemBufReg:            T_MipsWord;                   -- Memory buffer register
  signal  RxValidData:          booleans(0 to 1);             -- Valid flags for ISO buffers
  signal  EmptyPacket:          one_bit;                      -- Empty packet transfer
  signal  write_pkt_length_I:   boolean;                      -- Write packet lenght
  begin

    RxDataAccepted    <=  RxDataAccepted_I;
    write_pkt_length  <=  write_pkt_length_I;
    
    process(clk) 
      variable   RxWrBufferNo:           int_RxAddrTableType; -- buffer index in RAM
      variable   RxRdBufferNo:           int_RxAddrTableType; -- buffer index in RAM
      variable   WriteRxHeader:          boolean;             -- write header for a buffer
      variable   RxWrAdPointer:          Int_RxRamType;       -- RAM write address pointer
      variable   RxRdAdPointer:          Int_RxRamType;       -- RAM read address pointer
      variable   BufferFree:             boolean;             -- Buffer is available
      variable   RxError:                boolean;             -- Error in packet
      variable   DataToRam:              four_bytes;          -- Data to RAM
      variable   MemBufRegFull:          boolean;             -- memory buffer register is full
      variable   IsoEndPoint:            boolean;             -- ISO endpoint 
      variable   EmptyBuffer:            boolean;             -- No ISO packet from USB in the last frame
      -------------------------------------------------------------------------
      -- This function returns the index of buffer in RAM (RxWrBufferNo) 
      -- corresponding to a physical endpoint. The following table gives the 
      -- allocation of buffers for different endpoints. Bulk(Logical_EP: 3 OUT) 
      -- and ISO(Logical_EP: 4 OUT) endpoints are provided with double buffers.
      -- 
      -- Buffer_Number     Physical_EP     Logical_EP    Start_Address
      --     0              0                0 OUT           0 
      --     1              2                1 OUT           5 
      --     2              4                2 OUT           7 
      --     3              4                2 OUT           24 
      --     4              6                3 OUT           41 
      --     5              6                3 OUT           58 
      --     6              8                4 OUT           75 
      --     7              8                4 OUT           84 
      --------------------------------------------------------------------------
      procedure get_wr_buffer_index(Physical_EP: Int_EndPointType) is
         variable Logical_EP:  logical_ep_type;
        begin
          Logical_EP := physical_to_logical(Physical_EP);
          BufferFree := true;
          case Logical_EP is
    	when 0 =>  
    	    RxWrBufferNo := 0; 
    	when 1 =>  
    	    RxWrBufferNo := 1; 
    	when 2 =>  
    	if(USBToggleBuffer_Out(Physical_EP) = 0 and not FullBuffer_EP(Physical_EP)(0)) then 	
            RxWrBufferNo := 2; 		
        elsif(USBToggleBuffer_Out(Physical_EP) = 1 and not FullBuffer_EP(Physical_EP)(1)) then 	
            RxWrBufferNo := 3; 		
        else 					
            BufferFree := false; 		
        end if; 				
    	when 3 =>  
    	if(USBToggleBuffer_Out(Physical_EP) = 0 and not FullBuffer_EP(Physical_EP)(0)) then 	
            RxWrBufferNo := 4; 		
        elsif(USBToggleBuffer_Out(Physical_EP) = 1 and not FullBuffer_EP(Physical_EP)(1)) then 	
            RxWrBufferNo := 5; 		
        else 					
            BufferFree := false; 		
        end if; 				
    	when 4 =>  			
         if(PI_IsoToggle_Out = 0) then 		
            RxWrBufferNo := 6; 		
         else 					
            RxWrBufferNo := 7; 	
         end if; 				
      end case; 				
   end get_wr_buffer_index;  			

      -------------------------------------------------------------------------------
      -- This procedure leaves one location at the begining of a buffer in RAM 
      -- for writing header for the packet
      procedure RxleaveHeaderSpace is
        begin
          get_wr_buffer_index(EP_number_out);
          RxWrAdPointer := get_rx_buffer_address(RxWrBufferNo) + 1;
      end RxleaveHeaderSpace;
      -------------------------------------------------------------------------------
      -- This procedure puts data on RAM databus, address on RAM addressbus and makes 
      -- the Write Request signal high.
      -- Also it incriments the address counter.
      procedure RxRamWriteData (variable Data_in : in four_bytes) is
        begin
          RAMAddress_Wr    <= to_unsigned(RxWrAdPointer, RxRAMAddr_Width);
          RAM_WriteReq     <= true; 
          RAMData          <= Data_in;
          if(RxWrAdPointer = RxRamDepth - 1) then 
             RxWrAdPointer := 0;
          else
             RxWrAdPointer := RxWrAdPointer + 1;
          end if;
      end RxRamWriteData;
      ------------------------------------------------------------------------------
      -- This procedure recieves the data bytes from USB and writes into a 4-byte 
      -- wide register(Memory Buffer Register). After each byte is writen into the 
      -- MBR RxDataAccepted is asserted. Also leaves 1-word address space at the 
      -- begining of each RAM buffer
      procedure RxRamManager is
        variable DataToRam   : byte;
        begin
          -- leave one byte for the header in the beginning.
          if(RxDataCount = 0 and not RAM_WriteReq) then
             RxleaveHeaderSpace;
          end if;
          if(not MemBufRegFull) then
             MemBufReg(ByteCount) <= RxCore_Data;
             ByteCount            <= ByteCount + 1;
             RxDataAccepted_I     <= true;
             RxDataCount          <= RxDataCount + 1;
          end if; 
      end RxRamManager;
      -------------------------------------------------------------------------------
      -- This procedure writes header for a buffer in RAM. The header format is as
      -- shown below:
      -- Bit  31:           '1' Valid data '0' Corrupted data
      -- Bits 30 downto 10: Ignore (0's)
      -- Bits  9 downto  0: Packet size in Bytes
      -- For all packets except ISO, the size without any errors equals Rx_N_Data and
      -- with errors it is 0. For ISO, the size with error equals Rx_N_Data - 2 and 
      -- without eror it is equal to Rx_N_Data.

      procedure RxRamWriteHeader is
        begin   
          RxWrAdPointer := get_rx_buffer_address(RxWrBufferNo);
          DataToRam(30 DOWNTO 10) := (others => '0');
          RxDataCount <= 0;
          --IsoEndPoint := dma_endp_iso(EP_number_out);
          if(RxError and IsoEndPoint) then
             DataToRam(9 downto 0) := to_unsigned(Rx_N_Data - 2, 16)(9 downto 0);
          else
             DataToRam(9 downto 0) := to_unsigned(Rx_N_Data,16)(9 downto 0);