📄 usb_new_vsc9_ram_lfsr_c0.vhd
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zn => n000138);
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u000131: ni01d4
port map (i => n000036,
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u000132: ni01d4
port map (i => n000038,
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port map (a1 => n000082,
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port map (a1 => n000084,
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port map (a1 => n000085,
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u000144: xo02d1
port map (a1 => n000086,
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z => n000197);
u000145: xo02d1
port map (a1 => n000087,
a2 => n000018,
z => n000192);
u000146: xo02d1
port map (a1 => n000088,
a2 => n000019,
z => n000187);
u000147: xo02d1
port map (a1 => n000089,
a2 => n000020,
z => n000182);
u000148: xo02d1
port map (a1 => n000090,
a2 => n000021,
z => n000177);
u000149: xo02d1
port map (a1 => n000091,
a2 => n000022,
z => n000172);
u000150: xo02d1
port map (a1 => n000092,
a2 => n000023,
z => n000167);
u000151: xo02d1
port map (a1 => n000093,
a2 => n000024,
z => n000162);
u000152: xo02d1
port map (a1 => n000094,
a2 => n000025,
z => n000157);
u000153: xo02d1
port map (a1 => n000095,
a2 => n000026,
z => n000152);
u000154: xo02d1
port map (a1 => n000096,
a2 => n000027,
z => n000147);
u000155: xo02d1
port map (a1 => n000097,
a2 => n000028,
z => n000142);
u000156: xo02d1
port map (a1 => n000098,
a2 => n000029,
z => n000137);
u000157: xo02d1
port map (a1 => n000099,
a2 => n000030,
z => n000132);
u000158: xo02d1
port map (a1 => n000100,
a2 => n000031,
z => n000127);
u000159: xo02d1
port map (a1 => n000101,
a2 => n000032,
z => n000122);
u000160: xo02d1
port map (a1 => n000102,
a2 => n000033,
z => n000117);
u000161: xo02d1
port map (a1 => n000071,
a2 => n000035,
z => n000107);
u000162: xo03d1
port map (a1 => n000071,
a2 => n000076,
a3 => n000007,
z => n000247);
u000163: xo03d1
port map (a1 => n000071,
a2 => n000077,
a3 => n000008,
z => n000242);
u000164: xo03d1
port map (a1 => n000071,
a2 => n000103,
a3 => n000034,
z => n000112);
end STRUCTURAL; -- vsc9_ram_lfsr_c0
-- -----------------------------------------------------------------------------
-- vsc9_ram_lfsr_c0 : RTL VHDL
-- (RTL is optimized for simulation, not synthesis)
-- -----------------------------------------------------------------------------
--synopsys translate_off
architecture RTL of vsc9_ram_lfsr_c0 is
SIGNAL Q : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL D : STD_LOGIC_VECTOR(31 downto 0);
CONSTANT sreset_value : STD_LOGIC_VECTOR(31 downto 0) := "00000000000000000000000000000001";
begin
-- -----------------------------------------------------------------------------
toq : process (clk, D)
-- -----------------------------------------------------------------------------
begin
if (clk = '1' and clk'event) then
Q <= D;
end if;
end process;
-- -----------------------------------------------------------------------------
tod: process(Q, se, si, load, datain, csn, le, sig)
-- -----------------------------------------------------------------------------
begin
if (se = '1') then
D(31) <= si;
D(30 downto 0) <= Q(31 downto 1);
elsif (load = '1') then
D <= datain;
elsif (csn = '0') then
D <= sreset_value;
elsif (le = '0') then
D <= Q;
else
D <= Q(0)& Q(31 downto 1) xor sig(31 downto 0) xor '0'& Q(0)& "0000000000000000000000000"& Q(0)& Q(0)& "000";
end if;
end process;
so <= Q(0);
lout <= Q;
end RTL; -- vsc9_ram_lfsr_c0
--synopsys translate_on
-- -----------------------------------------------------------------------------
-- VHDL Component Instantiation:
-- -----------------------------------------------------------------------------
-- component vsc9_ram_lfsr_c0
-- port ( clk : in STD_LOGIC;
-- le : in STD_LOGIC;
-- csn : in STD_LOGIC;
-- sig : in STD_LOGIC_VECTOR(31 downto 0);
-- se : in STD_LOGIC;
-- si : in STD_LOGIC;
-- load : in STD_LOGIC;
-- datain : in STD_LOGIC_VECTOR(31 downto 0);
-- so : out STD_LOGIC;
-- lout : out STD_LOGIC_VECTOR(31 downto 0));
-- end component;
--
-- u1: vsc9_ram_lfsr_c0
-- port map ( clk => , -- Clock Input
-- le => , -- LFSR Enable Input
-- csn => , -- Clear Synchronous Not Input
-- sig => , -- 32 bit Signature Input
-- se => , -- Scan Select Input
-- si => , -- Scan in Input
-- load => , -- Load Select Input
-- datain => , -- 32 bit Parallel Data Load Input
-- so => , -- Scan Out Output
-- lout => ); -- 32 bit LFSR Output Result
-- -----------------------------------------------------------------------------
-- VHDL Synthesis Commands:
-- -----------------------------------------------------------------------------
-- set_dont_touch find(design, vsc9_ram_lfsr_c0, -hierarchy)
-- remove_attribute find(design, vsc9_ram_lfsr_c0, -hierarchy) dont_touch
-- set_ungroup find(design, vsc9_ram_lfsr_c0, -hierarchy)
-- -----------------------------------------------------------------------------
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