📄 usb_new_vsc9_ram_lfsr_c0.vhd
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-- HDLi Version 5.0 IP Bundle 2000.12.15
-- Top HDL file name is usb_new.vhd
-- -----------------------------------------------------------------------------
-- Royal Philips Electronics
-- -----------------------------------------------------------------------------
-- Copyright 2001 by Royal Philips Electronics All rights reserved.
--
-- This module is property of Royal Philips Electronics (Philips) and its use
-- is granted to the customer for the sole purpose of implementing in silicon
-- provided by Philips. This module may only be used in accordance with the
-- provisions of the HDLi License Agreement.
--
-- -----------------------------------------------------------------------------
-- USBFS22 Device Version 1.0
-- -----------------------------------------------------------------------------
-- usb_new/data/USBFS22/RTL/usb_new_vsc9_ram_lfsr_c0.vhd : RTL VHDL
--
-- Compiled by arkrish on Tue Apr 3 17:23:42 2001
-- -----------------------------------------------------------------------------
-- HDLi Version 5.0 IP Bundle 2000.12.15
-- Parameters: lfsr -b 32 -S -e -g -w 32 -L 3 -s 0x1 -l vsc983 -padlib cxxx_iolib -Synopsys -nrtl -nentity -nadd_p -ntiming -vhdl -verilog -Rarch RTL -Sarch STRUCTURAL -br 0,4,8,12,32,48 -ipnoprompt -ipchance medium
-- vsc9_ram_lfsr_c0: 560.67 physical gates (vsc983)
-- vsc9_ram_lfsr_c0: 14538.08 squm area (vsc983)
-- -----------------------------------------------------------------------------
-- Royal Philips Electronics
-- -----------------------------------------------------------------------------
-- Copyright 2001 by Royal Philips Electronics All rights reserved.
--
-- This module is property of Royal Philips Electronics (Philips) and its use
-- is granted to the customer for the sole purpose of implementing in silicon
-- provided by Philips. This module may only be used in accordance with the
-- provisions of the HDLi License Agreement.
--
-- -----------------------------------------------------------------------------
-- Linear Feedback Shift Register Function Compiler Version 1.1a
-- -----------------------------------------------------------------------------
-- vsc9_ram_lfsr_c0 : RTL & structural VHDL
-- (RTL is optimized for simulation, not synthesis)
--
-- Compiled by arkrish on Tue Apr 3 11:53:41 2001
-- -----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--synopsys translate_off
-- if trouble set hdlin_translate_off_skip_text = true
----use work.hdli.all;
library VLSI_DIVhdl;
use VLSI_DIVhdl.vlsidivhdl_package.all;
--synopsys translate_on
library work;
use work.hdli.all;
entity vsc9_ram_lfsr_c0 is
port ( clk : in STD_LOGIC;
le : in STD_LOGIC;
csn : in STD_LOGIC;
sig : in STD_LOGIC_VECTOR(31 downto 0);
se : in STD_LOGIC;
si : in STD_LOGIC;
load : in STD_LOGIC;
datain : in STD_LOGIC_VECTOR(31 downto 0);
so : out STD_LOGIC;
lout : out STD_LOGIC_VECTOR(31 downto 0));
end vsc9_ram_lfsr_c0;
architecture STRUCTURAL of vsc9_ram_lfsr_c0 is
component ni01d4
port ( i : in STD_LOGIC;
z : out STD_LOGIC);
end component;
component mfntnq2
port ( da : in STD_LOGIC;
db : in STD_LOGIC;
sa : in STD_LOGIC;
cp : in STD_LOGIC;
q : out STD_LOGIC);
end component;
component nd02d1
port ( a1 : in STD_LOGIC;
a2 : in STD_LOGIC;
zn : out STD_LOGIC);
end component;
component xo03d1
port ( a1 : in STD_LOGIC;
a2 : in STD_LOGIC;
a3 : in STD_LOGIC;
z : out STD_LOGIC);
end component;
component xo02d1
port ( a1 : in STD_LOGIC;
a2 : in STD_LOGIC;
z : out STD_LOGIC);
end component;
component fn05d1
port ( a1 : in STD_LOGIC;
b1 : in STD_LOGIC;
zn : out STD_LOGIC);
end component;
component mi21d1
port ( i0 : in STD_LOGIC;
i1 : in STD_LOGIC;
s : in STD_LOGIC;
zn : out STD_LOGIC);
end component;
component mx21d1
port ( i0 : in STD_LOGIC;
i1 : in STD_LOGIC;
s : in STD_LOGIC;
z : out STD_LOGIC);
end component;
component mfntnq1
port ( da : in STD_LOGIC;
db : in STD_LOGIC;
sa : in STD_LOGIC;
cp : in STD_LOGIC;
q : out STD_LOGIC);
end component;
signal n000266 : STD_LOGIC;
signal n000265 : STD_LOGIC;
signal n000264 : STD_LOGIC;
signal n000263 : STD_LOGIC;
signal n000262 : STD_LOGIC;
signal n000261 : STD_LOGIC;
signal n000260 : STD_LOGIC;
signal n000259 : STD_LOGIC;
signal n000258 : STD_LOGIC;
signal n000257 : STD_LOGIC;
signal n000256 : STD_LOGIC;
signal n000255 : STD_LOGIC;
signal n000073 : STD_LOGIC;
signal n000253 : STD_LOGIC;
signal n000252 : STD_LOGIC;
signal n000251 : STD_LOGIC;
signal n000250 : STD_LOGIC;
signal n000074 : STD_LOGIC;
signal n000248 : STD_LOGIC;
signal n000247 : STD_LOGIC;
signal n000246 : STD_LOGIC;
signal n000245 : STD_LOGIC;
signal n000075 : STD_LOGIC;
signal n000243 : STD_LOGIC;
signal n000242 : STD_LOGIC;
signal n000241 : STD_LOGIC;
signal n000240 : STD_LOGIC;
signal n000076 : STD_LOGIC;
signal n000238 : STD_LOGIC;
signal n000237 : STD_LOGIC;
signal n000236 : STD_LOGIC;
signal n000235 : STD_LOGIC;
signal n000077 : STD_LOGIC;
signal n000233 : STD_LOGIC;
signal n000232 : STD_LOGIC;
signal n000231 : STD_LOGIC;
signal n000230 : STD_LOGIC;
signal n000078 : STD_LOGIC;
signal n000228 : STD_LOGIC;
signal n000227 : STD_LOGIC;
signal n000226 : STD_LOGIC;
signal n000225 : STD_LOGIC;
signal n000079 : STD_LOGIC;
signal n000223 : STD_LOGIC;
signal n000222 : STD_LOGIC;
signal n000221 : STD_LOGIC;
signal n000220 : STD_LOGIC;
signal n000080 : STD_LOGIC;
signal n000218 : STD_LOGIC;
signal n000217 : STD_LOGIC;
signal n000216 : STD_LOGIC;
signal n000215 : STD_LOGIC;
signal n000081 : STD_LOGIC;
signal n000213 : STD_LOGIC;
signal n000212 : STD_LOGIC;
signal n000211 : STD_LOGIC;
signal n000210 : STD_LOGIC;
signal n000082 : STD_LOGIC;
signal n000208 : STD_LOGIC;
signal n000207 : STD_LOGIC;
signal n000206 : STD_LOGIC;
signal n000205 : STD_LOGIC;
signal n000083 : STD_LOGIC;
signal n000203 : STD_LOGIC;
signal n000202 : STD_LOGIC;
signal n000201 : STD_LOGIC;
signal n000200 : STD_LOGIC;
signal n000084 : STD_LOGIC;
signal n000198 : STD_LOGIC;
signal n000197 : STD_LOGIC;
signal n000196 : STD_LOGIC;
signal n000195 : STD_LOGIC;
signal n000085 : STD_LOGIC;
signal n000193 : STD_LOGIC;
signal n000192 : STD_LOGIC;
signal n000191 : STD_LOGIC;
signal n000190 : STD_LOGIC;
signal n000086 : STD_LOGIC;
signal n000188 : STD_LOGIC;
signal n000187 : STD_LOGIC;
signal n000186 : STD_LOGIC;
signal n000185 : STD_LOGIC;
signal n000087 : STD_LOGIC;
signal n000183 : STD_LOGIC;
signal n000182 : STD_LOGIC;
signal n000181 : STD_LOGIC;
signal n000180 : STD_LOGIC;
signal n000088 : STD_LOGIC;
signal n000178 : STD_LOGIC;
signal n000177 : STD_LOGIC;
signal n000176 : STD_LOGIC;
signal n000175 : STD_LOGIC;
signal n000089 : STD_LOGIC;
signal n000173 : STD_LOGIC;
signal n000172 : STD_LOGIC;
signal n000171 : STD_LOGIC;
signal n000170 : STD_LOGIC;
signal n000090 : STD_LOGIC;
signal n000168 : STD_LOGIC;
signal n000167 : STD_LOGIC;
signal n000166 : STD_LOGIC;
signal n000165 : STD_LOGIC;
signal n000091 : STD_LOGIC;
signal n000163 : STD_LOGIC;
signal n000162 : STD_LOGIC;
signal n000161 : STD_LOGIC;
signal n000160 : STD_LOGIC;
signal n000092 : STD_LOGIC;
signal n000158 : STD_LOGIC;
signal n000157 : STD_LOGIC;
signal n000156 : STD_LOGIC;
signal n000155 : STD_LOGIC;
signal n000093 : STD_LOGIC;
signal n000153 : STD_LOGIC;
signal n000152 : STD_LOGIC;
signal n000151 : STD_LOGIC;
signal n000150 : STD_LOGIC;
signal n000094 : STD_LOGIC;
signal n000148 : STD_LOGIC;
signal n000147 : STD_LOGIC;
signal n000146 : STD_LOGIC;
signal n000145 : STD_LOGIC;
signal n000095 : STD_LOGIC;
signal n000143 : STD_LOGIC;
signal n000142 : STD_LOGIC;
signal n000141 : STD_LOGIC;
signal n000140 : STD_LOGIC;
signal n000096 : STD_LOGIC;
signal n000138 : STD_LOGIC;
signal n000137 : STD_LOGIC;
signal n000136 : STD_LOGIC;
signal n000135 : STD_LOGIC;
signal n000097 : STD_LOGIC;
signal n000133 : STD_LOGIC;
signal n000132 : STD_LOGIC;
signal n000131 : STD_LOGIC;
signal n000130 : STD_LOGIC;
signal n000098 : STD_LOGIC;
signal n000128 : STD_LOGIC;
signal n000127 : STD_LOGIC;
signal n000126 : STD_LOGIC;
signal n000125 : STD_LOGIC;
signal n000099 : STD_LOGIC;
signal n000123 : STD_LOGIC;
signal n000122 : STD_LOGIC;
signal n000121 : STD_LOGIC;
signal n000120 : STD_LOGIC;
signal n000100 : STD_LOGIC;
signal n000118 : STD_LOGIC;
signal n000117 : STD_LOGIC;
signal n000116 : STD_LOGIC;
signal n000115 : STD_LOGIC;
signal n000101 : STD_LOGIC;
signal n000113 : STD_LOGIC;
signal n000112 : STD_LOGIC;
signal n000111 : STD_LOGIC;
signal n000110 : STD_LOGIC;
signal n000102 : STD_LOGIC;
signal n000108 : STD_LOGIC;
signal n000107 : STD_LOGIC;
signal n000106 : STD_LOGIC;
signal n000105 : STD_LOGIC;
signal n000103 : STD_LOGIC;
signal n000071 : STD_LOGIC;
signal n000070 : STD_LOGIC;
signal n000069 : STD_LOGIC;
signal n000068 : STD_LOGIC;
signal n000067 : STD_LOGIC;
signal n000066 : STD_LOGIC;
signal n000065 : STD_LOGIC;
signal n000064 : STD_LOGIC;
signal n000063 : STD_LOGIC;
signal n000062 : STD_LOGIC;
signal n000061 : STD_LOGIC;
signal n000060 : STD_LOGIC;
signal n000059 : STD_LOGIC;
signal n000058 : STD_LOGIC;
signal n000057 : STD_LOGIC;
signal n000056 : STD_LOGIC;
signal n000055 : STD_LOGIC;
signal n000054 : STD_LOGIC;
signal n000053 : STD_LOGIC;
signal n000052 : STD_LOGIC;
signal n000051 : STD_LOGIC;
signal n000050 : STD_LOGIC;
signal n000049 : STD_LOGIC;
signal n000048 : STD_LOGIC;
signal n000047 : STD_LOGIC;
signal n000046 : STD_LOGIC;
signal n000045 : STD_LOGIC;
signal n000044 : STD_LOGIC;
signal n000043 : STD_LOGIC;
signal n000042 : STD_LOGIC;
signal n000041 : STD_LOGIC;
signal n000040 : STD_LOGIC;
signal n000039 : STD_LOGIC;
signal n000038 : STD_LOGIC;
signal n000037 : STD_LOGIC;
signal n000036 : STD_LOGIC;
signal n000035 : STD_LOGIC;
signal n000034 : STD_LOGIC;
signal n000033 : STD_LOGIC;
signal n000032 : STD_LOGIC;
signal n000031 : STD_LOGIC;
signal n000030 : STD_LOGIC;
signal n000029 : STD_LOGIC;
signal n000028 : STD_LOGIC;
signal n000027 : STD_LOGIC;
signal n000026 : STD_LOGIC;
signal n000025 : STD_LOGIC;
signal n000024 : STD_LOGIC;
signal n000023 : STD_LOGIC;
signal n000022 : STD_LOGIC;
signal n000021 : STD_LOGIC;
signal n000020 : STD_LOGIC;
signal n000019 : STD_LOGIC;
signal n000018 : STD_LOGIC;
signal n000017 : STD_LOGIC;
signal n000016 : STD_LOGIC;
signal n000015 : STD_LOGIC;
signal n000014 : STD_LOGIC;
signal n000013 : STD_LOGIC;
signal n000012 : STD_LOGIC;
signal n000011 : STD_LOGIC;
signal n000010 : STD_LOGIC;
signal n000009 : STD_LOGIC;
signal n000008 : STD_LOGIC;
signal n000007 : STD_LOGIC;
signal n000006 : STD_LOGIC;
signal n000005 : STD_LOGIC;
signal n000004 : STD_LOGIC;
signal n000003 : STD_LOGIC;
signal n000002 : STD_LOGIC;
signal n000001 : STD_LOGIC;
signal vdd : STD_LOGIC;
signal vss : STD_LOGIC;
begin
vdd <= '1';
vss <= '0';
n000001 <= clk;
n000002 <= le;
n000003 <= csn;
n000035 <= sig(31);
n000034 <= sig(30);
n000033 <= sig(29);
n000032 <= sig(28);
n000031 <= sig(27);
n000030 <= sig(26);
n000029 <= sig(25);
n000028 <= sig(24);
n000027 <= sig(23);
n000026 <= sig(22);
n000025 <= sig(21);
n000024 <= sig(20);
n000023 <= sig(19);
n000022 <= sig(18);
n000021 <= sig(17);
n000020 <= sig(16);
n000019 <= sig(15);
n000018 <= sig(14);
n000017 <= sig(13);
n000016 <= sig(12);
n000015 <= sig(11);
n000014 <= sig(10);
n000013 <= sig(9);
n000012 <= sig(8);
n000011 <= sig(7);
n000010 <= sig(6);
n000009 <= sig(5);
n000008 <= sig(4);
n000007 <= sig(3);
n000006 <= sig(2);
n000005 <= sig(1);
n000004 <= sig(0);
n000036 <= se;
n000037 <= si;
n000038 <= load;
n000070 <= datain(31);
n000069 <= datain(30);
n000068 <= datain(29);
n000067 <= datain(28);
n000066 <= datain(27);
n000065 <= datain(26);
n000064 <= datain(25);
n000063 <= datain(24);
n000062 <= datain(23);
n000061 <= datain(22);
n000060 <= datain(21);
n000059 <= datain(20);
n000058 <= datain(19);
n000057 <= datain(18);
n000056 <= datain(17);
n000055 <= datain(16);
n000054 <= datain(15);
n000053 <= datain(14);
n000052 <= datain(13);
n000051 <= datain(12);
n000050 <= datain(11);
n000049 <= datain(10);
n000048 <= datain(9);
n000047 <= datain(8);
n000046 <= datain(7);
n000045 <= datain(6);
n000044 <= datain(5);
n000043 <= datain(4);
n000042 <= datain(3);
n000041 <= datain(2);
n000040 <= datain(1);
n000039 <= datain(0);
so <= n000071;
lout(31) <= n000103;
lout(30) <= n000102;
lout(29) <= n000101;
lout(28) <= n000100;
lout(27) <= n000099;
lout(26) <= n000098;
lout(25) <= n000097;
lout(24) <= n000096;
lout(23) <= n000095;
lout(22) <= n000094;
lout(21) <= n000093;
lout(20) <= n000092;
lout(19) <= n000091;
lout(18) <= n000090;
lout(17) <= n000089;
lout(16) <= n000088;
lout(15) <= n000087;
lout(14) <= n000086;
lout(13) <= n000085;
lout(12) <= n000084;
lout(11) <= n000083;
lout(10) <= n000082;
lout(9) <= n000081;
lout(8) <= n000080;
lout(7) <= n000079;
lout(6) <= n000078;
lout(5) <= n000077;
lout(4) <= n000076;
lout(3) <= n000075;
lout(2) <= n000074;
lout(1) <= n000073;
lout(0) <= n000071;
u000001: fn05d1
port map (a1 => n000265,
b1 => n000258,
zn => n000256);
u000002: fn05d1
port map (a1 => n000265,
b1 => n000253,
zn => n000251);
u000003: fn05d1
port map (a1 => n000265,
b1 => n000248,
zn => n000246);
u000004: fn05d1
port map (a1 => n000265,
b1 => n000243,
zn => n000241);
u000005: fn05d1
port map (a1 => n000265,
b1 => n000238,
zn => n000236);
u000006: fn05d1
port map (a1 => n000265,
b1 => n000233,
zn => n000231);
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