usb_new_usbvpb_top_ent.vhdl

实现USB接口功能的VHDL和verilog完整源代码

--------------------------------------------------------------------------------
--
--  P H I L I P S  C O M P A N Y  R E S T R I C T E D
--                                         
--  Copyright (c) 1998.                    
--
--  Philips Electronics N.V.
--
--  Philips Semiconductors
--  Interconnectivity and Processor Peripheral group
--  Bangalore,India
--
--  All rights reserved. Reproduction in whole or in part is prohibited
--  without the written permission of the copyright owner.
--
--------------------------------------------------------------------------------
--
--  File            : usb_new_usbvpb_top_ent.vhdl 
--
--  Module          : USBVPB_TOP
--
--  Project         : VPB bus Interface to USB 1.1 Device(USBFS22)
--
--  Author          :              
--
--  Description     : The entity of USBVPB_TOP block
--
--  Status          : 
--
--  Contact address : 
--
--------------------------------------------------------------------------------

--------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity USBVPB_TOP is
  port(
       -- Clocks 
       USB_MainClk:          in    std_logic;                      -- Main clock
       USB_NeedClk:          out   std_logic;                      -- USB needs clock
       USB_BitClk:           in    std_logic;                      -- Bit clock in
       USB_BitClk_Out:       out   std_logic;                      -- Bit clock out

       -- Connect
       USB_Connect_N:        out   std_logic;                      -- Controls switch for softconnect
       USB_VBus:             in    std_logic;                      -- Bus power is present
        
       -- Misc
       USB_TestMode:         in    std_logic;                      -- Select test mode
       USB_Test_Resetn:      in    std_logic;                      -- Resetn during test mode
       
       -- Suspend
       USB_Suspend:          out   std_logic;                      -- USB Suspend 

       -- VPB bus interface
       PSEL:                 in    std_logic;                      -- select
       PENABLE:              in    std_logic;                      -- enable
       PADDR:                in    std_logic_vector(7 downto 0);  -- address
       PWRITE:               in    std_logic;                      -- write/read
       PRESETn:              in    std_logic;                      -- reset
       PCLK:                 in    std_logic;                      -- clock
       PWDATA:               in    std_logic_vector(31 downto 0);  -- write data
       PRDATA:               out   std_logic_vector(31 downto 0);  -- read data
       PRDY:                 out   std_logic;                      -- ready
       -- Interrupt controller signals
       USB_Int_Req_Irq:      out   std_logic;                      -- Irq interrupt   
       USB_Int_Req_Fiq:      out   std_logic;                      -- Fiq interrupt
   
       -- Upstream port
       USB_UP_LED_N:         out   std_logic;                      -- LED 
       USB_UP_RxDM:          in    std_logic;                      -- Rx D-  
       USB_UP_RxDP:          in    std_logic;                      -- Rx D+  
       USB_UP_RxRCV:         in    std_logic;                      -- Rx RCV 
       USB_UP_TxDM:          out   std_logic;                      -- Tx D- 
       USB_UP_TxDP:          out   std_logic;                      -- Tx D+
       USB_UP_TxEnable_N:    out   std_logic;                      -- Tx Enable


        -- Test Control Block signals for BIST RAM
          scan_test	: in  std_logic;  -- Scan Test                    
          scanclock     : in  std_logic;  -- Scan Clock
          tck           : in  std_logic;  -- Test Clock
          ntrst         : in  std_logic;  -- Test Reset (active low)
          tbe           : in  std_logic;  -- Test BIST Enable
          trunbist      : in  std_logic;  -- Test BIST Run/hold
          tend          : out std_logic;  -- Test End
          dri           : in  std_logic;  -- Data Retention Input (global data retention ready)
          dro           : out std_logic;  -- Data Retention Output (local data retention ready)
          tseir     	: in  std_logic;  -- Debug Scan Enable Instruction Register
          tsedr     	: in  std_logic;  -- Debug Scan Enable Data Register
          tdi       	: in  std_logic_vector(2 downto 0);  -- Test Data Input
          tdo       	: out std_logic_vector(2 downto 0);  -- Test Data Output

       si:                   in    std_logic_vector(7 downto 0);   -- scan chain i/p
       so:                   out   std_logic_vector(7 downto 0);   -- scan chain o/p
       se:                   in    std_logic                      -- scan enable    
      );
end USBVPB_TOP;