usb_new_vsc9_ram.vhd

实现USB接口功能的VHDL和verilog完整源代码

                   pattern <= PAT_TYPE_00;
                   cycle_type <= RWR_CYCLE;
          when d2_r0d =>  
                   if (endofblock = '1' and run = '1') then
                      mainstate_next <= d2_r1d;  
                   end if;    
                   pattern <= PAT_TYPE_FF;
                   cycle_type <= RWR_CYCLE;
                   adir <= '0';
                   acnt <= '0';
                   acsn <= '1';
          when d2_r1d =>  
                   if (endofblock = '1' and run = '1') then
                      mainstate_next <= st_end;  
                   end if;   
                   pattern <= PAT_TYPE_00;
                   cycle_type <= RWR_CYCLE;
                   adir <= '0';
                   acsn <= '1';
          when st_end =>
	           mainstate_next <= st_done;
          when st_done => 
                   if (run = '0') then
                      mainstate_next <= st_idle;
                   end if;   
                   march_enable <= '0';
		   tend_alias <= '1';                   
	  when others =>  -- st_idle
                   if (run = '1') then
                      mainstate_next <= st_init;
                   end if;
                   march_enable <= '0'; 
         end case;    
  end process state_logic;
                  

-- -----------------------------------------------------------------------
-- MARCH State Machine
-- -----------------------------------------------------------------------
  mstate_register: process (tck, ntrst)
  begin
    if (ntrst = '0') then
      mstate <= IDLESTATE;
    elsif (tck = '1' and tck'event) then
      mstate <= mstate_next;
    end if;
  end process;


-- -----------------------------------------------------------------------
-- assign next state of the MARCH State Machine
-- -----------------------------------------------------------------------   
  mstate_logic: process (endofblock, cycle_type, mstate, march_enable, adir, mainstate)
  begin
    if (march_enable = '1') then     -- state can be changed if enabled 
      case mstate is
        when IDLESTATE => 
          if (cycle_type = W_CYCLE) then
            mstate_next <= WRITESTATE0;
          else 
            mstate_next <= FIRSTREADSTATE0;
          end if;   
        when WRITESTATE0 | WRITESTATE =>
          if (cycle_type = RWR_CYCLE) then
            mstate_next <= LASTREADSTATE;
          elsif (endofblock = '1') then
            mstate_next <= FIRSTREADSTATE0;
          elsif (cycle_type = RW_CYCLE) then
            mstate_next <= FIRSTREADSTATE;
          else
            mstate_next <= WRITESTATE;   
          end if;               
        when FIRSTREADSTATE0 | FIRSTREADSTATE =>
          mstate_next <= WRITESTATE;               
        when LASTREADSTATE =>
          if(endofblock = '0') then
            mstate_next <= FIRSTREADSTATE;
          elsif (mainstate = d2_r1d) then
            mstate_next <= IDLESTATE;
          elsif (adir = '1') then
            mstate_next <= FIRSTREADSTATE0;
          elsif (mainstate = d1_r1d) then
            mstate_next <= WRITESTATE0;
          else
            mstate_next <= FIRSTREADSTATE0;
          end if;
        when others =>
          mstate_next <= IDLESTATE;               
      end case;
    else 
      mstate_next <= mstate;  
    end if;
  end process;      

-- -----------------------------------------------------------------------
-- LFSRCSN (active-low lfsr reset)
-- -----------------------------------------------------------------------
  lfsrcsn_logic: process (ntck)
  begin
    if (ntck = '1' and ntck'event) then
      if (mainstate = st_init) then
        lfsrcsn <= '0';
      else 
        lfsrcsn <= '1';
      end if;
    end if;
  end process;

-- -----------------------------------------------------------------------
-- ENDOFBLOCK (end of a sequence block)
--    ENDOFBLOCK is active high when any march sequence,
--     like +(w0) or -(r1, w0, r0), is finished.
-- -----------------------------------------------------------------------
  output_logic: process (tci, cycle_type, mstate)
  begin
    case mstate is
      when WRITESTATE0 | WRITESTATE =>
        if ((cycle_type = W_CYCLE OR cycle_type = RW_CYCLE) AND tci = '1') then
          endofblock <= '1';
        else
          endofblock <= '0';
        end if;
      when LASTREADSTATE =>
        endofblock <= tci;
      when others => -- IDLESTATE, FIRSTREADSTATES
        endofblock <= '0';
    end case;
  end process;

-- -----------------------------------------------------------------------
-- HWE (host write enable)
-- -----------------------------------------------------------------------
  hweb_logic: process (ntck)
  begin
    if (ntck = '1' AND ntck'event) then
      if (mstate = WRITESTATE0 OR mstate = WRITESTATE) then
        hweb <= '0';  --write cycle
      else
        hweb <= '1';
      end if;
    end if;
  end  process;

-- -----------------------------------------------------------------------
-- CEN (address generator enable)
-- -----------------------------------------------------------------------
  cen_logic: process (cycle_type, mstate, lrun, endofblock, acnt)
  begin
    if (lrun = '1' AND endofblock = '0') then
      case mstate is
        when WRITESTATE =>
          if (cycle_type = W_CYCLE) then
            cen <= '1';
          else
            cen <= '0';
          end if;
        when FIRSTREADSTATE =>
          cen <= '1';
        when OTHERS => -- FIRSTREADSTATE0, WRITESTATE0, IDLESTATE
          cen <= acnt;
      end case;
    else
      cen <= '0';
    end if;
  end process;


-- -----------------------------------------------------------------------
-- CAPTURE (capture enable)
--    After each active memory read operation, CAPTURE
--    signal will be enabled. CAPTURE is used to capture
--    the memory output data to the signature analyzer.
-- -----------------------------------------------------------------------
  precapture_logic: process (tck)
  begin
    if (tck = '1' AND tck'event) then
      case mstate is
        when FIRSTREADSTATE0 | FIRSTREADSTATE | LASTREADSTATE =>
          precapture <= run;
        when others => -- WRITESTATES, IDLESTATE
          precapture <= '0';
      end case;
    end if;
  end process;

  capture_logic: process (ntck)
  begin
    if (ntck = '1' AND ntck'event) then
      capture <= precapture;
    end if;
  end process;

-- -----------------------------------------------------------------------
-- Registered Halt signal for single step mode
-- -----------------------------------------------------------------------
  halt_register: process (ntck)
  begin
    if (ntck = '1' AND ntck'event) then
      if (restart = '1' AND precapture = '1' AND dbg = '1' ) then
          halt <= '1';
      elsif (restart = '1' AND dbg = '1' ) then
          halt <= halt;
      else
        halt <= '0';
      end if;
    end if;
  end process;

-- -----------------------------------------------------------------------
-- Delay the pattern to the falling edge.
-- -----------------------------------------------------------------------
  pattern_reg: process (ntck, ntrst)
  begin
    if (ntrst = '0') then
      client_pattern <= "00";
    elsif (ntck = '1' AND ntck'event) then
        client_pattern <= pattern;
    end if;
  end process;

-- -----------------------------------------------------------------------
-- Delay idle signal to the falling edge.
-- -----------------------------------------------------------------------
  idle_reg: process (ntck, ntrst, mstate)
  begin
    if (ntrst = '0') then
      idle <= '1';
    elsif (ntck = '1' and ntck'event) then
      if (mstate = IDLESTATE) then
        idle <= '1';
      else
        idle <= '0';
      end if;
    end if;
  end process;

-- -----------------------------------------------------------------------
-- Select clients run signal.
-- -----------------------------------------------------------------------
  client_run_reg: process (ntrst, idle, tbe, trunbist)
  begin
    if (ntrst = '0') then
      client_run <= '0';
    else
      if (idle = '1') then
        client_run <= '0';
      else
        client_run <= tbe AND trunbist;
      end if;
    end if;
  end process;

-- -----------------------------------------------------------------------
-- debug instruction register
--    Scan in instruction code if TSEIR is enabled.
--    The data is scanned from MSB to LSB:
--                tdi -> ir1 -> ir0
--    Instruction code:
--      step mode:    ir1=1 and ir0=0
--      bypass mode:  ir1=0 and ir0=1
-- -----------------------------------------------------------------------
  instruction_register: process (tck, ntrst)
  begin
    if (ntrst = '0') then
      ir <= "00";
    elsif (tck = '1' AND tck'event) then
      if (tseir = '1') then
        ir <= tdi & ir(1);
      end if;
    end if;
  end process;

-- -----------------------------------------------------------------------
-- Negative-edge flip-flop for IR shift path
-- -----------------------------------------------------------------------
  irneg_logic: process (ntck, ntrst)
  begin
    if (ntrst = '0') then
      ir_neg <= '0';
    elsif (ntck = '1' AND ntck'event) then
      ir_neg <= ir(0);
    end if;
  end process;

-- -----------------------------------------------------------------------
-- TDO (data out in the scan path)
-- -----------------------------------------------------------------------
  tdo_logic: process (tseir, tsedr, tdi, tend_alias, ir_neg)
  begin
    if (tseir = '1') then
      tdo <= ir_neg;
    elsif (tsedr = '0') then
      tdo <= tdi and tend_alias;
    else
      tdo <= tdi;
    end if;
  end process;

end RTL; --vsc9_ram.vhd 
-- -----------------------------------------------------------------------------
-- VHDL Component Instantiation:
-- -----------------------------------------------------------------------------
-- component vsc9_ram
--    port ( tck       : in STD_LOGIC;
--           ntrst     : in STD_LOGIC;
--           tbe       : in STD_LOGIC;
--           trunbist  : in STD_LOGIC;
--           tseir     : in STD_LOGIC;
--           tsedr     : in STD_LOGIC;
--           tdi       : in STD_LOGIC;
--           tdo       : out STD_LOGIC;
--           tend      : out STD_LOGIC;
--           chb       : out STD_LOGIC_VECTOR(15 downto 0);
--           dri       : in STD_LOGIC;
--           dro       : out STD_LOGIC);
-- end component;

--
-- u1: vsc9_ram
--    port map ( tck       => ,      -- Test Clock
--               ntrst     => ,      -- Test Reset (active low)
--               tbe       => ,      -- Test BIST Enable
--               trunbist  => ,      -- Test BIST Run/hold
--               tseir     => ,      -- Debug Scan Enable Instruction Register
--               tsedr     => ,      -- Debug Scan Enable Data Register
--               tdi       => ,      -- Test Data Input
--               tdo       => ,      -- Test Data Output
--               tend      => ,      -- Test End
--               chb       => ,      -- Client Host Bus
--               dri       => ,      -- Data Retention Input (global data retention ready)
--               dro       => );     -- Data Retention Output (local data retention ready)
-- -----------------------------------------------------------------------------