📄 usb_new_vsc9_ram.vhd
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-- HDLi Version 5.0 IP Bundle 2000.12.15
-- Top HDL file name is usb_new.vhd
-- -----------------------------------------------------------------------------
-- Royal Philips Electronics
-- -----------------------------------------------------------------------------
-- Copyright 2001 by Royal Philips Electronics All rights reserved.
--
-- This module is property of Royal Philips Electronics (Philips) and its use
-- is granted to the customer for the sole purpose of implementing in silicon
-- provided by Philips. This module may only be used in accordance with the
-- provisions of the HDLi License Agreement.
--
-- -----------------------------------------------------------------------------
-- USBFS22 Device Version 1.0
-- -----------------------------------------------------------------------------
-- usb_new/data/USBFS22/RTL/usb_new_vsc9_ram.vhd : RTL VHDL
--
-- Compiled by arkrish on Tue Apr 3 17:23:42 2001
-- -----------------------------------------------------------------------------
-- HDLi Version 5.0 IP Bundle 2000.12.15
-- Parameters: bistsram -t 0 -p -LFSR24 -instname '' -L.num 2 -L0.d 96 -L0.b 32
-- -L0.r 0 -L0.n 'spram96x32' -L1.d 96 -L1.b 32 -L1.r 0 -L1.n 'spram96x32' -l
-- vsc983 -padlib cxxx_iolib -Synopsys -nrtl -nentity -nadd_p -ntiming -vhdl
-- -verilog -Rarch RTL -Sarch STRUCTURAL -br 0,4,8,12,32,48 -ipnoprompt
-- -ipchance medium
-- -----------------------------------------------------------------------------
-- Royal Philips Electronics
-- -----------------------------------------------------------------------------
-- Copyright 2001 by Royal Philips Electronics All rights reserved.
--
-- This module is property of Royal Philips Electronics (Philips) and its use
-- is granted to the customer for the sole purpose of implementing in silicon
-- provided by Philips. This module may only be used in accordance with the
-- provisions of the HDLi License Agreement.
--
-- -----------------------------------------------------------------------------
-- BIST SRAM Template Version 2.4
-- -----------------------------------------------------------------------------
-- vsc9_ram.vhd : RTL VHDL
--
-- Compiled by arkrish on Tue Apr 3 11:53:35 2001
-- -----------------------------------------------------------------------------
--
-- Option Value
-- ------ -----
-- Interface: Serial/IEEE1149.1
-- Provide Data Retention Synchronizer? Yes
-- Minimum LFSR Width: 24 bits
-- Client: 0
-- Client Depth: 96
-- Client Width: 32
-- RAM Type: VSMXXRS111 (HDI Single Port Synchronous RAM)
-- Output Enable Pin? No
-- RAM Name: spram96x32
-- Client: 1
-- Client Depth: 96
-- Client Width: 32
-- RAM Type: VSMXXRS111 (HDI Single Port Synchronous RAM)
-- Output Enable Pin? No
-- RAM Name: spram96x32
--
-- -----------------------------------------------------------------------------
-- Functional Description:
--
-- The BIST circuitry employs the March C+ algorithm for the primary port
-- in the register file, and the March C- algorithm for the other ports.
-- Results are captured via the signature analyzer. This is a synchronous
-- design using one clock domain to facilitate scan insertion. The BIST host
-- block references the following modules:
-- top level ____ bist state machine
-- |__ pattern generator ____ march controller
-- |__ address generator
-- -----------------------------------------------------------------------------
-- Limitations: None known at this time.
-- -----------------------------------------------------------------------------
-- Critical Timing: main state machine -> address generator
-- -----------------------------------------------------------------------------
-- Non-Portable Instantiations: None
-- -----------------------------------------------------------------------------
-- Targeted Technologies: vsc883
-- -----------------------------------------------------------------------------
-- Author: System Technology Creation Date: May 1, 1997
-- -----------------------------------------------------------------------------
-- Revision History:
-- 1.0 8/97 Initial Release
-- -----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Host BIST (Top Level)
----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
----use work.vsc9_ram_pkg.all;
----use work.vsc9_ram_addressor_pkg.all;
library work;
use work.vsc9_ram_pkg.all;
use work.all;
entity vsc9_ram is
port ( tck : in std_logic; -- Test Clock
ntrst : in std_logic; -- Test Reset (active low)
tbe : in std_logic; -- Test BIST Enable
trunbist : in std_logic; -- Test BIST Run/hold
tseir : in std_logic; -- Debug Scan Enable Instruction Register
tsedr : in std_logic; -- Debug Scan Enable Data Register
tdi : in std_logic; -- Test Data Input
tdo : out std_logic; -- Test Data Output
tend : out std_logic; -- Test End
chb : out std_logic_vector(15 downto 0); -- Client Host Bus
dri : in std_logic; -- Data Retention Input (global data retention ready)
dro : out std_logic); -- Data Retention Output (local data retention ready)
end vsc9_ram;
architecture RTL of vsc9_ram is
component vsc9_ram_addressor
port ( clk : in std_logic;
csn : in std_logic;
cen : in std_logic;
up : in std_logic;
q : out std_logic_vector(6 downto 0);
tci : out std_logic);
end component;
signal mainstate: STATE_TYPE; -- present bist sequence state
signal mainstate_next: STATE_TYPE; -- next bist sequence state
signal mstate: STD_LOGIC_VECTOR(2 downto 0); -- March state
signal mstate_next: STD_LOGIC_VECTOR(2 downto 0); -- next state of mstate
signal march_enable: STD_LOGIC; -- march controller enable
signal cycle_type: STD_LOGIC_VECTOR(1 downto 0); -- type of cycle w,rw,rwr
signal endofblock: STD_LOGIC; -- End of a March
signal idle: STD_LOGIC; -- mstate in idlestate
signal ir: STD_LOGIC_VECTOR(1 downto 0); -- instruction register
signal ir_neg: STD_LOGIC; -- negative edge value of IR lsb
signal dbg: STD_LOGIC; -- debug signal
signal halt: STD_LOGIC; -- halt run signal
signal ntck: STD_LOGIC; -- inverted tck
signal acsn: STD_LOGIC; -- address clear sync not
signal cen: STD_LOGIC; -- addressor count enable
signal acnt: STD_LOGIC; -- address count enable from SM
signal adir: STD_LOGIC; -- address direction
signal tci: STD_LOGIC; -- terminal count indicator of the address
signal haddr: STD_LOGIC_VECTOR(MAXADDRBITS-1 downto 0); -- address bus
signal hweb: STD_LOGIC; -- write enable
signal pattern: STD_LOGIC_VECTOR(1 downto 0); -- data pattern
signal run: STD_LOGIC; -- run enable
signal lrun: STD_LOGIC; -- latched run enable
signal restart: STD_LOGIC; -- latched restart signal
signal precapture:STD_LOGIC; -- precapture enable
signal capture: STD_LOGIC; -- capture enable
signal lfsrcapture: STD_LOGIC; -- capture into the signature enable
signal lfsrload: STD_LOGIC; -- capture into the LFSR register enable
signal lfsrcsn: STD_LOGIC; -- clear LFSR sync not
signal client_run: STD_LOGIC; -- client run enable
signal client_shift: STD_LOGIC; -- client shift enable
signal bypass: STD_LOGIC; -- bypass mode
signal client_pattern:STD_LOGIC_VECTOR(1 downto 0);
signal idro: STD_LOGIC; -- internal data retention output
signal tend_alias:STD_LOGIC; -- internal tend
begin
ntck <= not(tck);
dbg <= ir(1);
bypass <= ir(0);
lfsrcapture <= capture AND not(dbg);
lfsrload <= capture AND dbg;
run <= tbe and trunbist and not(halt) and (not(idro) or dri) and not(bypass);
dro <= idro OR bypass;
client_shift <= tsedr AND not(bypass);
tend <= tend_alias;
-- -----------------------------------------------------------------------
-- CHB (client host bus)
-- CHB provides control signals for the client.
-- -----------------------------------------------------------------------
chb <= haddr & client_pattern & hweb & client_shift &
client_run & lfsrload & lfsrcapture & lfsrcsn & tbe;
-- -----------------------------------------------------------------------
-- Address Counter
-- -----------------------------------------------------------------------
uaddr: vsc9_ram_addressor
port map (clk => ntck,
csn => acsn,
cen => cen,
up => adir,
q => haddr,
tci => tci);
-- -----------------------------------------------------------------------
-- Data Retention output generation
-- -----------------------------------------------------------------------
dro_process: process (ntck, ntrst)
begin
if (ntrst = '0') then
idro <= '0';
elsif (ntck = '1' and ntck'event) then
if ((mainstate = d1_r1u OR mainstate = d1_r0d) AND endofblock = '1') then
idro <= '1';
else
idro <= '0';
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- RUN (run signal sampled on the rising edge, used by falling edge stuff)
-- -----------------------------------------------------------------------
lrun_register: process (tck, ntrst)
begin
if (ntrst = '0') then
lrun <= '0';
elsif (tck = '1' and tck'event) then
lrun <= run;
end if;
end process;
-- -----------------------------------------------------------------------
-- RESTART (signal used in on falling edge in debug mode)
-- -----------------------------------------------------------------------
restart_register: process (tck)
begin
if (tck = '1' and tck'event) then
restart <= trunbist and tbe;
end if;
end process;
-- -----------------------------------------------------------------------
-- MAIN STATE MACHINE
-- -----------------------------------------------------------------------
state_register: process (tck, ntrst)
begin
if (ntrst = '0') then
mainstate <= st_idle;
elsif (tck = '1' and tck'event) then
if (run = '1' OR mainstate = st_done ) then
mainstate <= mainstate_next;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- assign NEXTSTATE and control signals
-- -----------------------------------------------------------------------
state_logic: process (mainstate, endofblock, run, mstate, adir)
begin
-- Defaults
tend_alias <= '0';
pattern <= PAT_TYPE_55;
if (mstate = FIRSTREADSTATE0) then
acsn <= '0';
else
acsn <= '1';
end if;
if (mstate = FIRSTREADSTATE0 AND adir = '0') then
acnt <= '1';
else
acnt <= '0';
end if;
adir <= '1';
cycle_type <= W_CYCLE;
march_enable <= run;
mainstate_next <= mainstate;
case (mainstate) is
when st_init =>
mainstate_next <= d1_w0;
acsn <= '0';
when d1_w0 =>
if (endofblock = '1' and run = '1') then
mainstate_next <= d1_r0u;
end if;
pattern <= PAT_TYPE_55;
cycle_type <= W_CYCLE;
when d1_r0u =>
if (endofblock = '1' and run = '1') then
mainstate_next <= d1_r1u;
end if;
pattern <= PAT_TYPE_AA;
cycle_type <= RWR_CYCLE;
when d1_r1u =>
if (endofblock = '1' and run = '1') then
mainstate_next <= d1_r0d;
end if;
pattern <= PAT_TYPE_55;
cycle_type <= RWR_CYCLE;
when d1_r0d =>
if (endofblock = '1' and run = '1') then
mainstate_next <= d1_r1d;
end if;
pattern <= PAT_TYPE_AA;
cycle_type <= RWR_CYCLE;
adir <= '0';
acnt <= '0';
acsn <= '1';
when d1_r1d =>
if (endofblock = '1' and run = '1') then
mainstate_next <= d2_w0;
end if;
pattern <= PAT_TYPE_55;
cycle_type <= RWR_CYCLE;
adir <= '0';
acsn <= '1';
when d2_w0 =>
if (endofblock = '1' and run = '1') then
mainstate_next <= d2_r0u;
end if;
pattern <= PAT_TYPE_00;
cycle_type <= W_CYCLE;
when d2_r0u =>
if (endofblock = '1' and run = '1') then
mainstate_next <= d2_r1u;
end if;
pattern <= PAT_TYPE_FF;
cycle_type <= RWR_CYCLE;
when d2_r1u =>
if (endofblock = '1' and run = '1') then
mainstate_next <= d2_r0d;
end if;
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