usb_new_uc_handler_ent.vhdl

实现USB接口功能的VHDL和verilog完整源代码

---------------------------------------------------------------------------------------------
---- File >>> usb_new_uc_handler_ent.vhdl 
---- Iden >>>							980317-11:42:38
----
---- Project:           USB Developement
---- Customer:          Philips_ITCL
----
---- VHDL Design Unit:  entity UC_HANDLER
---- Written by:        Usb User
----                    Easics nv
----                    http://www.easics.com      
----                    mailto: [e-mail]
----
---- Creation Date:     Tue, 17 Mar 1998
----
---- Purpose:
----
---- Revision history:
----
---------------------------------------------------------------------------------------------
      
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

library work;
use work.PCK_GENERAL.all;
use work.PCK_USB.all;
use work.PCK_HANDLERS.all;
use work.PCK_CONFIGURATION.all;
use work.PCK_SETUP.all;

library work;
USE work.PCK_APB.ALL;


entity UC_HANDLER is

  generic (
           ID: integer := 0
          ); 
  
  port (
        --- Signals to and from Controller ---
        DataFromUC:     in T_UC_to_Handlers;   -- Data from Uc
        DataToUC_In:    in T_Handlers_to_UC;   -- uC ring, entering module
        DataToUC_Out:   out T_Handlers_to_UC;  -- uC ring, leaving module 

        ---------- Signals to other USBINT blocks ------------
        RG_SetSE0Int:         in  boolean;          -- Received bus reset
        HC_ResetDevice:       in  booleans(N_EMBEDDED_PORTS -1 downto 0); -- HUB requests a device reset
        DH_Connect:           IN  boolean;  -- Pullups on.          
        
        ---   Connection to SIE Interface   ---

        DataFromHandlers_In:    in  T_Handlers_to_SIE;  -- SIE ring, entering module 
        DataFromHandlers_Out:  out  T_Handlers_to_SIE;  -- SIE ring, leaving module 
        DataToHandlers:         in  T_SIE_to_Handlers;  -- Data from SIEInterface 
	
	    ---   Connection to PI_HANDLER ---
        Uc_To_Pi:               out  T_UC_to_pi_handler;
        Pi_To_Uc:               in   T_pi_to_uc_handler;
        Sie_Read:               out  one_bit;
        Sie_Write:              out  one_bit;   
        SIE_EndTransfer:        out  one_bit;
        RxError_SIE:            out  boolean; 
        Start_In_Transfer:      out  one_bit;
        N_Data_EP :             in   nine_bits;
        SIE_N_Data:             out  integer range 0 to MAX_OVERFLOW_SIZE;
        EPBufferInfo:           out  T_EPBufferInfo;

	-- Interface to TIMERS_SF
	TM_IsoToggle:           in  integer range 0 to 1;
        
        ---------- System --------------------------------
        TestMode:            in    one_bit; -- active high
        ConfigArray:          in S_ConfigArray;   -- Configuration Array
        PUReset_N:            in  one_bit;         -- Asynchr. power up reset
        FsClk:                in  one_bit          -- Recovered Clock
       );

end UC_HANDLER;