usb_new_clkrec_ent.vhdl

实现USB接口功能的VHDL和verilog完整源代码

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---- File >>> usb_new_clkrec_ent.vhdl 
---- Iden >>>							951017-16:10:15
----
---- Project:		USB Development
---- Customer:		Philips_ITCL
----
---- Module:		entity CLKREC
---- Written by:	Jan Decaluwe (e-mail: [e-mail])
----			Easics nv
----			Kapeldreef 60
----			B-3001	Leuven
----			Belgium
----			Tel [phone]
----			Fax [phone]
----			e-mail: [e-mail]
----
---- Creation Date:	Tue, 17 Oct 1995
----
---- Purpose:
----
---- Revision history:
----
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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

library work;
use work.PCK_GENERAL.all;
use work.PCK_USB.all;

entity CLKREC is

  port  (
	  ---  Input from Hub or Upstream Port  ---
	  HB_UsbDifBit:      in  one_bit;   --  Differential Usb input
	  HB_UsbLineBits:    in  two_bits;  --  Single ended Usb inputs

	  ---  Output to SIE  ---
	  CR_UsbLineBits:    out two_bits;  --  Dplus and Dmin for SIE

	  ---  For Debugging  ---
          CR_DebugRecDataP:  out one_bit;   --  Dplus for debugging
          CR_DebugRecDataN:  out one_bit;   --  Dmin for debugging

	  ---  Clock Outputs  ---
	  Clk12MHz_O:        out one_bit;   --  Recovered clock
	  Clk12MHzRef_O:     out one_bit;   --  Reference clock

	  ---  Enable Signal  ---
	  SIE_CREnable:      in  boolean;   --  Enable clock recovery

	  ---  Suspend Input  ---
	  TM_Suspend:        in  boolean;   --  Suspend

	  ---  System  ---
	  Clk48MHz:          in  one_bit;   --  48 MHz clock
	  Reset48MHz_N:      in  one_bit;   --  Reset for 48 MHz clock
          PU_Reset_N:        in  one_bit    --  Power On Reset
	);

end CLKREC;