usb_new_upstreamled_ent.vhdl

实现USB接口功能的VHDL和verilog完整源代码

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---- File >>> usb_new_upstreamled_ent.vhdl 
---- Iden >>>							980306-10:26:00
----
---- Project:           USB Development
---- Customer:          Philips_ITCL
----
---- VHDL Design Unit:  
---- Written by:        Usb User
----                    Easics nv
----                    http://www.easics.com      
----                    mailto: [e-mail]
----
---- Creation Date:     Fri, 06 Mar 1998
----
---- Purpose:
----
---- Revision history:
----
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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

library work;
use work.PCK_GENERAL.all;
use work.PCK_USB.all;
use work.PCK_CONFIGURATION.all;

entity UPSTREAMLED is
  port  (
       --- LED control ---
       Configured_LED:     out one_bit; -- LED output

       --- Device State  ---
       SH_Succes:          in boolean; -- Successful transfer
       SH_Configured:      in boolean; -- Device is configured
       TM_Suspend:         in boolean; -- Device is suspended

       --- from timers ---
       TM_1kHzPulse:       in one_bit; -- 1 kHz clock pulse
       
       --- system ---
       ConfigArray:        in S_ConfigArray; -- Configuration info
       FsClk:              in one_bit; -- Recovered clock
       Reset_N:            in one_bit -- Reset for Recovered clock
	);
end UPSTREAMLED;