usb_new_usb_int_ent.vhdl

实现USB接口功能的VHDL和verilog完整源代码

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--
--  P H I L I P S  C O M P A N Y  R E S T R I C T E D
--                                         
--  Copyright (c) 1998.                    
--
--  Philips Electronics N.V.
--
--  Philips Semiconductors
--  Interconnectivity and Processor Peripheral group
--  Bangalore,India
--  All rights reserved. Reproduction in whole or in part is prohibited
--  without the written permission of the copyright owner.
--
--------------------------------------------------------------------------------
--
--  File            : usb_new_usb_int_ent.vhdl 
--
--  Module          : USB_INT
--
--  Project         : VPB bus Interface to USB 1.1 Device(USBFS22)
--
--  Author          :              
--
--  Description     : The entity of USB_INT module
--
--  Status          : 
--
--  Contact address : 
--
--------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

library work;
use work.PCK_GENERAL.all;
use work.PCK_CONFIGURATION.all;
use work.PCK_SETUP.all;
use work.PCK_HANDLERS.all;
use work.PCK_USB.all;

library work;
use work.PCK_APB.all ;

entity USB_INT is
     port(
          -- APB interface
          clk:                      in  one_bit;                -- PVCI clock
          pvci_reset_n:             in  one_bit;                -- Reset
          req:                      in  one_bit;                -- Request
          address:                  in  byte;                   -- Address
          rnw:                      in  one_bit;                -- '0' write, '1' read
          w_data:                   in  four_bytes;             -- Write data
          gnt:                      out one_bit;                -- Grant
          r_data:                   out four_bytes;             -- Read data
          error:                    out one_bit;                -- Error
       
          -- Interrupt signals
          Intr_Request_Irq:         out one_bit;                -- Irq Interrupt request to processor
          Intr_Request_Fiq:         out one_bit;                -- Fiq Interrupt request to processor
 
 
          -- Clock Outputs
          Clk12MHzRef_O:            out one_bit;                -- Reference clock
          Clk12MHz_O:               out one_bit;                -- Recovered clock

          -- Configuration Info
          ChipID:                    in S_ChipID;               -- Chip ID
          ConfigArray:              out S_ConfigArray;          -- Configuration Info
          PINConfigArray:            in S_PINConfigArray;       -- Configuration Info from pins

          -- Connection to RX RAM
          RxRAM_E_N:                out one_bit;                -- RAM enable, active low
          RxRAM_W_N:                out one_bit;                -- RAM write, active low
          RxRAM_G_N:                out one_bit;                -- RAM grant(read), active low
          RxRAM_A:                  out RxRAMAddr_bits;         -- RAM address bus
          RxRAM_DQ_In:               in four_bytes;             -- RAM data in-bus
          RxRAM_DQ_Out:             out four_bytes;             -- RAM data out-bus
          
          -- Connection to TX RAM
          TxRAM_E_N:                out one_bit;                -- RAM enable, active low
          TxRAM_W_N:                out one_bit;                -- RAM write, active low
          TxRAM_G_N:                out one_bit;                -- RAM grant(read), active low
          TxRAM_A:                  out TxRAMAddr_bits;         -- RAM address bus
          TxRAM_DQ_In:               in four_bytes;             -- RAM data in-bus
          TxRAM_DQ_Out:             out four_bytes;             -- RAM data out-bus

          -- Control Signals
          SIE_LowSpeedTransaction:  out boolean;                -- Packet preceded by preamble
          SIE_RxUsbLogValue:        out T_UsbLog_enum;          -- Debugging

          -- Device State
          DH_Interrupt:             out boolean;                -- Change Notification to uC

          -- For Debugging
          CR_DebugRecDataN:         out one_bit;                -- Dmin for debugging
          CR_DebugRecDataP:         out one_bit;                -- Dplus for debugging

          -- Frame Timer
          TM_EOF2:                  out boolean;                -- Fixed to FALSE (used for hub devices)

          -- Generated reset signals
          RG_BUSReset:              out boolean;                -- Bus Reset
          Reset12MHzRef_N:          out one_bit;                -- referential clock
          USB_Reset_O_N:            out one_bit;                -- to controller

          -- Input from Hub or Upstream Port
          HB_UsbDifBit:              in one_bit;                -- Differential Usb input
          HB_UsbLineBits:            in two_bits;               -- Single ended Usb inputs

          -- Inputs
          PU_Reset_N:                in one_bit;                -- power up reset
          UP_DsLineBits:             in two_bits;               -- downstream USB bus

          -- LED control
          Configured_LED:           out one_bit;                -- LED output

          -- Signals to other USB_PVCI blocks
          HC_ResetDevice:            in booleans(N_EMBEDDED_PORTS -1 downto 0); -- HUB requests a device reset

          -- Soft Connect
          DH_Connect:               out boolean;                -- Resistor Switch Control
          VBusAvailable:             in boolean;                -- VBus is available

          -- Suspend/Wake up
          EX_NeedClock:              in boolean;                -- Optional module needs clock
          RemoteWakeup:              in boolean;                -- Send remote wakeup
          Suspend_In:                in boolean;                -- Suspend input
          TM_ClockOn:               out one_bit;                -- Clock control
          TM_ClockRestarted:        out boolean;                -- Pulse after clock restart
          TM_Idle5ms:               out boolean;                -- Device is idle for more than 5 ms
          USB_Suspended:            out one_bit;                -- Device is suspended

          -- system
          Clk12MHzRef:               in one_bit;                -- 12 MHz reference clock
          Clk48MHz:                  in one_bit;                -- 48 MHz clock

          -- System
          FsClk:                     in one_bit;                -- Bit Clock
          TM_IsoToggle:             out integer range 0 to 1;   -- toggling iso buffers
          TestMode:                  in one_bit;                -- Testmode input
          USB_FrameClock:           out one_bit;                -- 1 kHz frame clock

          -- To USB bus
          SIE_TxLogValue:           out T_UsbLog_enum;          -- Data to Send
          SIE_UsbEnable_N:          out one_bit                 -- Transmit Enable
         );
end USB_INT;