usb_new_usb_cntrl_ent.vhdl

实现USB接口功能的VHDL和verilog完整源代码

-------------------------------------------------------------------------------
--  Copyright (c) 1998.
--
--  Philips Electronics N.V.
--
--  Philips Semiconductors
--  Interconnectivity and Processor Peripheral group
--  Bangalore, India
--  All rights reserved. Reproduction in whole or in part is prohibited
--  without the written permission of the copyright owner.
--
--------------------------------------------------------------------------------
--
--  File            : usb_new_usb_cntrl_ent.vhdl 
--
--  Module          : USB controller
--
--  Project         : VPB bus interface to USB 1.1 device (USBFS22)
--
--  Author          :
--
--  Description     : The entity of USB controller
--
--  Contact address : [e-mail]
--
--------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

library work;
use work.PCK_GENERAL.all;
use work.PCK_HANDLERS.all;

library work;
use work.PCK_APB.all;

entity USB_CNTRL is
 port(
       -- Interface to PVCI_CONTROLLER

       Write_Cmd_Code:         in  one_bit;          -- Write command register
       Write_Transmt_Data:     in  one_bit;          -- Write transmit data register
       Write_Intr_Enable:      in  one_bit;          -- Write interrupt enable register
       Write_Intr_Clear:       in  one_bit;          -- Write interrupt clear register
       Write_Intr_Set:         in  one_bit;          -- Write interrupt set register
       Write_TxPkt_Lngth:      in  one_bit;          -- Write Tx packet length register
       Write_Usb_Cntrl:        in  one_bit;          -- Write USB control register
       Read_Cmd_Data:          in  one_bit;          -- Read command data
       Read_Receive_Data:      in  one_bit;          -- Read receive data
       Read_Intr_Status:       in  one_bit;          -- Read interrupt status register
       Read_Intr_enable:       in  one_bit;          -- Read interrupt enable register
       Read_RxPkt_Lngth:       in  one_bit;          -- Read rx packet length register
       Read_Usb_Cntrl:         in  one_bit;          -- Read USB control register
       Read_TxPkt_Lngth:       in  one_bit;          -- Read Tx packet length register
       Wr_Data:                in  four_bytes;       -- Write data
       Rd_Data:                out four_bytes;       -- Read data
       Error:                  in  one_bit;          -- Wrong register address
       Write_Fiq_Sel:          in  one_bit;          -- Write Fiq sel register
       
       -- Interrupt signals

       Intr_Request_Irq:       out one_bit;          -- Irq Interrupt request to processor
       Intr_Request_Fiq:       out one_bit;          -- Fiq Interrupt request to processor

       -- Interface to RCV_RAM

       DataFromRam:            in  four_bytes;       -- Data from Recieve RAM
       RxRam_Read:             out one_bit;          -- Receive RAM read
       Rx_Pkt_End:             out one_bit;          -- Rx packet read end
       Endpoint_Nr:            out logical_ep_type;  -- Logical endpoint number
       write_pkt_length:       in  boolean;          -- write packet length
       
       -- Interface to TRNSMT_RAM

       TxRam_write:            out one_bit;          -- Receive RAM write
       DataToRam:              out four_bytes;       -- Data to Receive RAM
       Tx_Pkt_End:             out one_bit;          -- Tx packet write end  
       Packet_Length:          out ten_bits;         -- Number of bytes for IN packet
       -- Interface to SYNCHRONIZER module

       CommandDataChannel:     in  byte;             -- Command data
       CmdDataValid_Out:       in  boolean;          -- Command data valid           
       CmdAccept_Out:          in  boolean;          -- Command code accepted
       CommandCode:            out eleven_bits;      -- Command code
       CmdCodeValid:           out boolean;          -- Command code valid
       EndTransfer_Cmd_D:      in  one_bit;          -- End of command data transfer
       USBEp0IntrSet:          in  one_bit;          -- USB Ep0 interrupt
       USBEp1IntrSet:          in  one_bit;          -- USB Ep1 interrupt
       USBEp2IntrSet:          in  one_bit;          -- USB Ep2 interrupt
       USBEp3IntrSet:          in  one_bit;          -- USB Ep3 interrupt
       USBEp4IntrSet:          in  one_bit;          -- USB Ep4 interrupt
       USBEp5IntrSet:          in  one_bit;          -- USB Ep5 interrupt
       USBEp6IntrSet:          in  one_bit;          -- USB Ep6 interrupt
       USBEp7IntrSet:          in  one_bit;          -- USB Ep7 interrupt
       USBDevIntrSet:          in  one_bit;          -- USB Dev interrupt
       FrameIntr_Set:          in  one_bit;          -- Frame interrupt
       USBToggleBuffer_Out:    in  T_ToggleArray;    -- USB buffer toggle
       FullBuffer_EP:          in  T_Full;           -- Buffer full for endpoints
       
       -- Clock and reset from system

       pvci_reset_n:           in  one_bit;
       Clk:                    in  one_bit
       );
 end USB_CNTRL;