usb_new_trnsmt_ram_ent.vhdl

实现USB接口功能的VHDL和verilog完整源代码

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--
--  P H I L I P S  C O M P A N Y  R E S T R I C T E D
--                                         
--  Copyright (c) 1998.                    
--                                           
--  Philips Electronics N.V.                   
--                                           
--  Philips Semiconductors                 
--  Interconnectivity and Processor Peripheral group                          
--  Bangalore, India                           
--  All rights reserved. Reproduction in whole or in part is prohibited
--  without the written permission of the copyright owner.
--
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--
--  File            : usb_new_trnsmt_ram_ent.vhdl 
--
--  Module          : Transmit RAM Manager
--
--  Project         : VPB bus interface to USB 1.1 device (USBFS22)
--
--  Author          :            
--
--  Description     : The entity of Transmit RAM manager block 
-- 
--  Contact address : [e-mail]
--
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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

library work;
use work.PCK_GENERAL.all;
use work.PCK_HANDLERS.all;

library work;
use work.PCK_APB.all; 

entity TRNSMT_RAM  is
       port(
            -- Interface to SYNCHRONIZER module

            UCToggleBuffer_Out:  in    T_ToggleArray;           -- UC toggle buffer
            USBToggleBuffer_Out: in    T_ToggleArray;           -- USB toggle buffer
            FullBuffer_EP:       in    T_Full;                  -- Full buffer for all endpoints
            PI_IsoToggle_Out:    in    integer range 0 to 1;    -- ISO toggle buffer
            start_in_tx:         in    one_bit;                 -- Start of IN transfer
            TxDest_Endp:         in    Int_EndPointType;        -- Physical endpoint number
            Read_Data:           in    one_bit;                 -- Read data
            End_Transfer_D:      in    one_bit;                 -- End of packet data transfer

            -- Interface to EP_HANDLER module

            Read_Req:            out   one_bit;                 -- ????
            Data_In:             out   byte;                    -- Data bus for IN data
            TxDest_NData:        out   nine_bits;               -- Number of bytes for IN packet

            -- Interface to USB_CONTROLLER module

            Packet_Length:       in    ten_bits;                -- Number of bytes for IN packet
            TxRam_Write:         in    one_bit;                 -- Write into RAM
            EndPoint_Nr:         in    logical_ep_type;         -- Logical endpoint number
            DataToRam:           in    four_bytes;              -- Data word to RAM
            Tx_Pkt_End:          in    one_bit;                 -- End of packet is reached

            -- Interface to TRNSMT_RAM module

            TxRAM_E_N:           out   one_bit;                 -- RAM enable, active low
            TxRAM_W_N:           out   one_bit;                 -- RAM write, active low
            TxRAM_G_N:           out   one_bit;                 -- RAM grant(read), active low
            TxRAM_A:             out   TxRAMAddr_bits;          -- RAM address bus
            TxRAM_DQ_In:         in    four_bytes;              -- RAM data in-bus
            TxRAM_DQ_Out:        out   four_bytes;              -- RAM data out-bus
            
            -- Clock and reset from system

            clk:                 in    one_bit;                 -- APB bus clock
            pvci_reset_n:        in    one_bit                  -- APB bus reset
           );
  end  TRNSMT_RAM;