usb_new_trnsmt_ram_rtl.vhdl

实现USB接口功能的VHDL和verilog完整源代码

        variable Logical_EP: logical_ep_type;
      begin
        Logical_EP := physical_to_logical(Physical_EP);
        case Logical_EP is
    	when 0 =>  
     		TxRdBufferNo := 0; 
    	when 1 =>  
     		TxRdBufferNo := 1; 
    	when 2 =>  
    	if(USBToggleBuffer_Out(Physical_EP) = 0 and FullBuffer_EP(Physical_EP)(0)) then 
        	TxRdBufferNo := 2; 	
        elsif(USBToggleBuffer_Out(Physical_EP) = 1 and FullBuffer_EP(Physical_EP)(1)) then 
        	TxRdBufferNo := 3; 	
        end if; 			
    	when 3 =>  
    	if(USBToggleBuffer_Out(Physical_EP) = 0 and FullBuffer_EP(Physical_EP)(0)) then 
        	TxRdBufferNo := 4; 	
        elsif(USBToggleBuffer_Out(Physical_EP) = 1 and FullBuffer_EP(Physical_EP)(1)) then 
        	TxRdBufferNo := 5; 	
        end if; 			
    	when 4 =>  			
        if(PI_IsoToggle_Out = 0) then 		
        	TxRdBufferNo := 6; 		
        else 					
        	TxRdBufferNo := 7; 	
        end if; 				
     end case; 					
  end get_rd_buffer_index; 			
      ------------------------------------------------------------------------------
      -- This procedure puts the address on Ram bus and requests for Ram read
      -- Also it increments the Read address pointer
      procedure TxRamReadData is
      begin
        TxRamAddr_Read <= to_unsigned(TxRdAdPointer, TxRAMAddr_Width);
        TxRam_Read <= true;
        RamDataReady <= false;
        if(TxRdAdPointer = TxRamDepth - 1) then
           TxRdAdPointer := 0;
        else
           TxRdAdPointer := TxRdAdPointer + 1;
        end if;
      end TxRamReadData;
      ------------------------------------------------------------------------------
      -- This procedure loads the read address pointer with the start address of a
      -- buffer and requsets RAM reading
      procedure TxRdProgress is
      begin
        get_rd_buffer_index(TxDest_Endp);
        ReadHeaderWord <= true;  
        TxRdAdPointer := get_tx_buffer_address(TxRdBufferNo);   
        TxRamReadData; 
        TransferProgress := true;
      end TxRdProgress;
      -------------------------------------------------------------------------------
      -- This procedure controls the reading of data from RAM in response to IN
      -- request from USB
      procedure TxRamReadManager is
      begin
        if(RamDataReady) then
           if(ReadHeaderWord) then
              N_Data := to_integer(MemBufReg(1)(0) & MemBufReg(0));
              TxCoreNDataReg(8 downto 0) <= MemBufReg(1)(0) & MemBufReg(0);
              TxRamReadData; 
              ProceedRead <= true; 
              ReadHeaderWord  <= false; 
              ByteCount <= 0;
           elsif(not TxCoreDataRegFull and ProceedRead)then    
              if(N_Data = 0) then
                 ProceedRead <= false;
                 TransferProgress := false;
                 ByteCount <= 0;
                 RamDataReady <= false;
                 TxCoreNDataReg <= (others => '0');
              else 
                 TxCoreDataReg <= MemBufReg(ByteCount);
                 Read_Req_I     <= '1';
                 TxCoreDataRegFull := true;
                 N_Data :=  N_Data - 1;
                 if(ByteCount = 3) then
                    ByteCount <= 0;
                    if(N_Data > 0) then
                       TxRamReadData;
                    end if;
                 else
                    ByteCount <= ByteCount + 1;
                 end if;  
              end if; 
           end if; 
        end if;                 
      end TxRamReadManager;
      ------------------------------------------------------------------------------------

      begin
        if(clk'event AND clk = '1') then           
          -- Synchronous reset for all registers
          if(pvci_reset_n = '0') then
             TxDataCount           <=  0;              
             RAMData               <= (others => '0');
             WriteTxHeader         <= false;
             RAMAddress_Wr         <= (others => '0');
             RAMData               <= (others => '0');
             TxWrAdPointer         := 0;
             TxWrBufferNo          := 0;
             TxRdBufferNo          := 0;
             BufferFree            := true;
             TransferProgress      := false; 
             Read_Req_I            <= '0';
             TxCoreDataReg         <= (others => '0');
             ProceedRead           <= false;
             TxCoreNDataReg        <= (others => '0');
             TxCoreDataRegFull     := false;
             TxRdAdPointer         := 0;
             ReadHeaderWord        <= false;
             RamDataReady          <= false;
             TxRam_Read             <= false;
             ByteCount             <= 0;
             TxRamAddr_Read        <= (others => '0');
             MemBufReg             <= (others => (others => '0')); 
             N_Data                := 0;

          else
             -- RAM Write related logic
             if(TxRam_Write = '1' or WriteTxHeader) then
                if(TxRam_Write = '1') then
                   TxRamWriteManager;
                elsif(WriteTxHeader) then
                   TxRamWriteHeader;
                end if;
                --RAM_WriteGrant <= true;
                RAMWrite_Req <= true;
             else
                --RAM_WriteGrant <= false;
                RAMWrite_Req <= false;
             end if;
             if(Tx_Pkt_End = '1') then
               WriteTxHeader <= true;              
             end if;
             --RAMAddress_Wr  <= to_unsigned(TxWrAdPointer, TxRAMAddr_WIDTH);

             -- RAM Read related logic
             if(TxRAM_ReadGrant) then
                MemBufReg(0) <= TxRAM_DQ_In(7 downto 0);
                MemBufReg(1) <= TxRAM_DQ_In(15 downto 8);
                MemBufReg(2) <= TxRAM_DQ_In(23 downto 16);
                MemBufReg(3) <= TxRAM_DQ_In(31 downto 24);               
                RamDataReady <= true;
                TxRam_Read  <= false;
             end if;
             if(start_in_tx = '1') then
                TxRdProgress;
             end if;
             if(TransferProgress) then
                TxRamReadManager;
             end if;
             if(Read_Data = '1') then
                TxCoreDataRegFull := false;
             end if;
             if(End_Transfer_D = '1') then
                TransferProgress := false;
                TxCoreDataRegFull := false;
                Read_Req_I <= '0';
                RamDataReady <= false;
		ProceedRead <= false;
             end if;
             if(not TxCoreDataRegFull) then
                Read_Req_I <= '0';
             end if;
          end if;
        end if;
    end process;
    
    -- RAM arbitrer
    RAM_WriteGrant   <= RAMWrite_Req;
    TxRAM_ReadGrant  <= TxRam_Read and (not RAMWrite_Req);
    RAMAddress       <= RAMAddress_Wr when RAM_WriteGrant else TxRamAddr_Read;
    Write            <= '1' when RAM_WriteGrant else '0';
    TxRAM_A          <= RAMAddress;
    TxRAM_W_N        <= Not(Write);
    TxRAM_G_N        <= Not(clk);   
    TxRAM_DQ_Out     <= RAMData;
    TxRAM_E_N        <= pvci_reset_n; 
   end RTL;