usb_new_trnsmt_ram_rtl.vhdl

实现USB接口功能的VHDL和verilog完整源代码

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--
--  P H I L I P S  C O M P A N Y  R E S T R I C T E D
--                                         
--  Copyright (c) 1998.                    
--  
--  Philips Electronics N.V 
--  
--  Philips Semiconductors
--  Intrconnectivity and Processor Peripherals group  
--  Bangalore, India                   
--  All rights reserved. Reproduction in whole or in part is prohibited
--  without the written permission of the copyright owner.
--
--------------------------------------------------------------------------------
--
--  File            : usb_new_trnsmt_ram_rtl.vhdl 
--
--  Module          : Transmit RAM Manager
--
--  Project         : VPB bus interface to USB 1.1 device (USBFS22)
--
--  Author          :             
--
--  Description     : The Architecture of Transmit RAM manager block 
--
--  Contact address : [e-mail]
--
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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

library work;
use work.PCK_GENERAL.all;

library work;
use work.PCK_APB.all; 

architecture RTL of TRNSMT_RAM is

  signal  TxDataCount:          Int_CountDatatype;               -- Count number of bytes written into RAM
  signal  RAMAddress_Wr:        TxRAMAddr_bits;                  -- RAM write address 
  signal  TxRamAddr_Read:       TxRAMAddr_bits;                  -- RAM read address 
  signal  RAMAddress:           TxRAMAddr_bits;                  -- RAM addrss
  signal  RAM_WriteGrant:       boolean;                         -- RAM write grant
  signal  RAMWrite_Req:         boolean;                         -- RAM write request
  signal  write:                one_bit;                         -- RAM write 
  signal  RAMData:              four_bytes;                      -- RAM data
  signal  WriteTxHeader:        boolean;                         -- Write RAM header
  signal  DataToRam_Int:        four_bytes;                      -- Data to RAM 
  signal  Read_Req_I:           one_bit;                         -- ????
  signal  ReadHeaderWord:       boolean;                         -- Read Header word   
  signal  TxCoreDataReg:        byte;                            -- Data byte read from RAM
  signal  RamDataReady:         boolean;                         -- RAM data ready
  signal  ProceedRead:          boolean;                         -- Read data byte from RAM
  signal  TxCoreNDataReg:       nine_bits;                       -- Number of bytes for IN packet
  signal  MemBufReg:            T_MipsWord;                      -- Data word read from RAM
  signal  ByteCount:            Int_TwoBits;                     -- Byte counter
  signal  TxRam_Read:           boolean;                         -- RAM read request
  signal  TxRAM_ReadGrant:      boolean;                         -- RAM read grant
  begin   
    TxDest_NData <= TxCoreNDataReg;
    Data_In      <= TxCoreDataReg;
    Read_Req     <= Read_Req_I;
    
    process(clk) 
      variable   TxWrAdPointer:          Int_TxRamType;
      variable   TxRdBufferNo:           Int_TxAddrTableType;
      variable   TxWrBufferNo:           Int_TxAddrTableType;
      variable   BufferFree:             boolean;
      variable   TransferProgress:       boolean;
      variable   TxCoreDataRegFull:      boolean;
      variable   TxRdAdPointer:          Int_TxRamType;
      variable   N_Data:                 Int_countDataType;
      variable   DataTo_Ram : four_bytes;
      -------------------------------------------------------------------------
      -- This function returns the index of buffer in RAM (TxWrBufferNo)
      -- corresponding to a physical endpoint. The following table gives the
      -- allocation of buffers for different endpoints. Bulk(Logical_EP: 3 OUT)
      -- and ISO(Logical_EP: 4 OUT) endpoints are provided with double buffers.
      --
      -- Buffer_Number     Physical_EP     Logical_EP    Start_Address
      --     0              1               0 OUT          0 
      --     1              3               1 OUT          5 
      --     2              5               2 OUT          10 
      --     3              5               2 OUT          27 
      --     4              7               3 OUT          44 
      --     5              7               3 OUT          61 
      --     6              9               4 OUT          78 
      --     7              9               4 OUT          87 
      -------------------------------------------------------------------------
      procedure get_wr_buffer_index(Logical_EP: in logical_ep_type) is
       variable Physical_EP: Int_EndPointType;
       begin
         BufferFree := true;
         Physical_EP := logical_to_physical(Logical_EP,'1');
         case Logical_EP is
    	when 0 =>  
    		TxWrBufferNo := 0; 
    	when 1 =>  
    		TxWrBufferNo := 1; 
    	when 2 =>  
     	if(UCToggleBuffer_Out(Physical_EP) = 0 and not FullBuffer_EP(Physical_EP)(0) ) then 
		TxWrBufferNo := 2; 
     	elsif(UCToggleBuffer_Out(Physical_EP) = 1 and not FullBuffer_EP(Physical_EP)(1) ) then 
	 	TxWrBufferNo := 3; 
     	else 
	 	BufferFree := false; 
    	end if; 
    	when 3 =>  
     	if(UCToggleBuffer_Out(Physical_EP) = 0 and not FullBuffer_EP(Physical_EP)(0) ) then 
		TxWrBufferNo := 4; 
     	elsif(UCToggleBuffer_Out(Physical_EP) = 1 and not FullBuffer_EP(Physical_EP)(1) ) then 
	 	TxWrBufferNo := 5; 
     	else 
	 	BufferFree := false; 
    	end if; 
    	when 4 =>  				
        if(PI_IsoToggle_Out = 1) then 		
		TxWrBufferNo := 6; 			
	else 					
		TxWrBufferNo := 7; 		
	end if; 				
     end case; 					
  end get_wr_buffer_index; 			
      --------------------------------------------------------------------------
      -- This procedure leaves one location at the begining of a buffer in RAM
      -- for writing header for the packet
      procedure  TxleaveHeaderSpace  is
      begin
        get_wr_buffer_index(Endpoint_nr);
        TxWrAdPointer := get_tx_buffer_address(TxWrBufferNo) + 1;
      end TxleaveHeaderSpace;
      ---------------------------------------------------------------------------
      -- This procedure puts data on RAM databus, address on RAM addressbus and makes
      -- the Write Request signal high.
      procedure TxRamWriteData (variable Data_in : in four_bytes) is
      begin
        RAMAddress_Wr  <= to_unsigned(TxWrAdPointer, TxRAMAddr_WIDTH);
        RAMData        <= Data_in;
        if(TxWrAdPointer = TxRamDepth - 1) then
           TxWrAdPointer := 0;
        else
           TxWrAdPointer := TxWrAdPointer + 1;
        end if;
      end TxRamWriteData;
      -----------------------------------------------------------------------------
      -- This procedure writes the data into RAM
      procedure  TxRamWriteManager is
        variable DataTo_Ram : four_bytes;
      begin
        -- leave one byte for the header in the beginning.
        -- Write new data if previous Data is written
        if(TxDataCount = 0) then
           TxleaveHeaderSpace;
        end if; 
	DataTo_Ram := DataToRam;
        TxRamWriteData(DataTo_Ram);
        TxDataCount <= TxDataCount + 4;
      end TxRamWriteManager;
      ------------------------------------------------------------------------------
      -- This procedure writes header for a buffer in RAM. The header format is as
      -- shown below:
      -- Bits 31 downto 10: Ignore (0's)
      -- Bits  9 downto  0: Packet size in Bytes
      -- Also it generates validate buffer signals for all endpoints 
      procedure TxRamWriteHeader is
        --variable DataTo_Ram : four_bytes;
      begin   
        TxWrAdPointer := get_tx_buffer_address(TxWrBufferNo);
        RAMAddress_Wr  <= to_unsigned(TxWrAdPointer, TxRAMAddr_WIDTH);
        DataTo_Ram(31 downto 10) := (others => '0');
        DataTo_Ram(9 downto 0) := Packet_Length;
        TxRamWriteData(DataTo_Ram);
        BufferFree := false;
        WriteTxHeader <= false; 
        TxDataCount <= 0;
      end TxRamWriteHeader;
      ------------------------------------------------------------------------------
      -- This function returns the index of buffer in RAM (TxRdBufferNo)
      -- corresponding to a physical endpoint. 
      procedure get_rd_buffer_index(Physical_Ep: in Int_EndPointType) is