usb_new_pvci_eng_str.vhdl

实现USB接口功能的VHDL和verilog完整源代码

                                 
       RxDataAccepted            =>          RxDataAccepted,
       RxCore_Data               =>          RxCore_Data,
       EP_number_Out             =>          EP_number_Out,
       End_Transfer_D            =>          End_Transfer_D,
       RxError_Out               =>          RxError_Out,
       USBToggleBuffer_Out       =>          USBToggleBuffer_Out,
       UCToggleBuffer_Out        =>          UCToggleBuffer_Out,
       FullBuffer_EP             =>          FullBuffer_EP,
       PI_IsoToggle_Out          =>          PI_IsoToggle_Out,
      
       -- Interface to TRNSMT_RAM                   

       Read_Data                 =>         Read_Data,
       start_in_tx               =>         start_in_tx,
       TxDest_Endp               =>         TxDest_Endp,

       -- Clock and Reset from APB                   

       clk                       =>         clk,
       pvci_reset_n              =>         pvci_reset_n
      );

   RCV_RAM_1: RCV_RAM
   port map
      (
       -- Interface to SYNCHRONIZER

       If_Busy                   =>         If_Busy_i,
       RxCore_Data               =>         RxCore_Data,
       EP_number_out             =>         EP_number_out,
       Rx_N_data                 =>         Rx_N_data,
       End_Transfer_D            =>         End_Transfer_D,
       RxError_Out               =>         RxError_Out,
       FullBuffer_EP             =>         FullBuffer_EP,
       USBToggleBuffer_Out       =>         USBToggleBuffer_Out,
       UCToggleBuffer_Out        =>         UCToggleBuffer_Out,
       PI_IsoToggle_Out          =>         PI_IsoToggle_Out,
       RxDataAccepted            =>         RxDataAccepted,

       -- Interface to RAM                 
                                
       RxRAM_DQ_In               =>         RxRAM_DQ_In,
       RxRAM_E_N                 =>         RxRAM_E_N,
       RxRAM_W_N                 =>         RxRAM_W_N,
       RxRAM_G_N                 =>         RxRAM_G_N,
       RxRAM_A                   =>         RxRAM_A,
       RxRAM_DQ_Out              =>         RxRAM_DQ_Out,
                                

       -- Interface to USB_CNTRL
                
       DataFromRam               =>         DataFromRam,
       RxRam_Read                =>         RxRam_Read,
       Rx_Pkt_End                =>         Rx_Pkt_End,
       EndPoint_Nr               =>         EndPoint_Nr,
       write_pkt_length          =>         write_pkt_length,
                                 
       -- Clock and reset from PVCI_CNTRL                

       clk                       =>         clk,
       pvci_reset_n              =>         pvci_reset_n
      );

   TRNSMT_RAM_1: TRNSMT_RAM
   port map
      (
       -- Interface to SYNHRONIZER          

       UCToggleBuffer_Out        =>         UCToggleBuffer_Out,
       USBToggleBuffer_Out       =>         USBToggleBuffer_Out,
       FullBuffer_EP             =>         FullBuffer_EP,
       PI_IsoToggle_Out          =>         PI_IsoToggle_Out,
       start_in_tx               =>         start_in_tx,
       TxDest_Endp               =>         TxDest_Endp,
       Read_Data                 =>         Read_Data,
       End_Transfer_D            =>         End_Transfer_D,

       -- Interface to EP_HANDLER

       Read_Req                  =>         Read_Req,
       Data_In                   =>         Data_In,
       TxDest_NData              =>         TxDest_NData,

       -- Interface to USB_CNTRL                

       Packet_Length             =>         Packet_Length,
       TxRam_Write               =>         TxRam_Write,
       EndPoint_Nr               =>         EndPoint_Nr,
       DataToRam                 =>         DataToRam,
       Tx_Pkt_End                =>         Tx_Pkt_End,

       -- Interface to TX_RAM

       TxRAM_E_N                 =>         TxRAM_E_N,
       TxRAM_W_N                 =>         TxRAM_W_N,
       TxRAM_G_N                 =>         TxRAM_G_N,
       TxRAM_A                   =>         TxRAM_A,
       TxRAM_DQ_In               =>         TxRAM_DQ_In,
       TxRAM_DQ_Out              =>         TxRAM_DQ_Out,

       -- Clock and reset from PVCI_CNTRL                  

       clk                       =>         clk,
       pvci_reset_n              =>         pvci_reset_n
      );

   USB_CNTRL_1: USB_CNTRL
   port map
      (
       -- Interface to PVCI_CNTRL

       Write_Cmd_Code            =>         Write_Cmd_Code,
       Write_Transmt_Data        =>         Write_Transmt_Data,
       Write_Intr_Enable         =>         Write_Intr_Enable,
       Write_Intr_Clear          =>         Write_Intr_Clear,
       Write_Intr_Set            =>         Write_Intr_Set,
       Write_TxPkt_Lngth         =>         Write_TxPkt_Lngth,
       Write_Usb_Cntrl           =>         Write_Usb_Cntrl,
       Write_Fiq_Sel             =>         Write_Fiq_Sel,
       Read_Usb_Cntrl            =>         Read_Usb_Cntrl,
       Read_Cmd_Data             =>         Read_Cmd_Data,
       Read_Receive_Data         =>         Read_Receive_Data,
       Read_Intr_Status          =>         Read_Intr_Status,
       Read_Intr_enable          =>         Read_Intr_enable,
       Read_RxPkt_Lngth          =>         Read_RxPkt_Lngth,
       Read_TxPkt_Lngth          =>         Read_TxPkt_Lngth,
       Wr_Data                   =>         Wr_Data,
       Rd_Data                   =>         Rd_Data,
       Error                     =>         Error_int,

       -- Interface to RCV_RAM

       DataFromRam               =>         DataFromRam,
       RxRam_Read                =>         RxRam_Read,
       Rx_Pkt_End                =>         Rx_Pkt_End,
       Endpoint_Nr               =>         Endpoint_Nr,
       write_pkt_length          =>         write_pkt_length,

       -- Interface to TRNSMT_RAM

       TxRam_write               =>         TxRam_write,
       DataToRam                 =>         DataToRam,
       Tx_Pkt_End                =>         Tx_Pkt_End,
       Packet_length             =>         Packet_Length,

       -- Interface to SYNCHRONIZER

       CommandDataChannel        =>         CommandDataChannel,
       CmdDataValid_Out          =>         CmdDataValid_Out,
       CmdAccept_Out             =>         CmdAccept_Out,
       CommandCode               =>         CommandCode,
       CmdCodeValid              =>         CmdCodeValid,
       EndTransfer_Cmd_D         =>         EndTransfer_Cmd_D,
       USBEp0IntrSet             =>          USBEp0IntrSet,
       USBEp1IntrSet             =>          USBEp1IntrSet,
       USBEp2IntrSet             =>          USBEp2IntrSet,
       USBEp3IntrSet             =>          USBEp3IntrSet,
       USBEp4IntrSet             =>          USBEp4IntrSet,
       USBEp5IntrSet             =>          USBEp5IntrSet,
       USBEp6IntrSet             =>          USBEp6IntrSet,
       USBEp7IntrSet             =>          USBEp7IntrSet,
       USBDevIntrSet             =>          USBDevIntrSet,       
       FrameIntr_Set             =>         FrameIntr_Set,
       USBToggleBuffer_Out       =>         USBToggleBuffer_Out,
       FullBuffer_EP             =>         FullBuffer_EP,

       -- Interrupt signals to system

       Intr_Request_Irq          =>         Intr_Request_Irq,
       Intr_Request_Fiq          =>         Intr_Request_Fiq,
                                 
       -- Clock and reset from PVCI_CNTRL
                                 
       pvci_reset_n              =>         pvci_reset_n,
       clk                       =>         clk
      );

   PVCI_CNTRL_1: PVCI_CNTRL
   port map
      (
       -- Interface to APB_WRAPPER
 
       clk                       =>         clk,
       pvci_reset_n              =>         pvci_reset_n,
       req                       =>         req,
       address                   =>         address,
       rnw                       =>         rnw,
       w_data                    =>         w_data,
       gnt                       =>         gnt,
       r_data                    =>         r_data,
       error                     =>         error_int,

       -- Interface to USB_CNTRL

       Rd_data                   =>        Rd_data,
       Write_Cmd_Code            =>        Write_Cmd_Code,
       Read_Cmd_Data             =>        Read_Cmd_Data,
       Read_Receive_Data         =>        Read_Receive_Data,
       Write_Transmt_Data        =>        Write_Transmt_Data,
       Write_USB_Cntrl           =>        Write_USB_Cntrl,
       Read_USB_Cntrl            =>        Read_USB_Cntrl,
       Read_RxPkt_Lngth          =>        Read_RxPkt_Lngth,
       Write_TxPkt_Lngth         =>        Write_TxPkt_Lngth,
       Read_Intr_Status          =>        Read_Intr_Status,
       Read_Intr_enable          =>        Read_Intr_enable,
       Write_Intr_Enable         =>        Write_Intr_Enable,
       Write_Intr_Clear          =>        Write_Intr_Clear,
       Write_Intr_Set            =>        Write_Intr_Set,
       Write_Fiq_Sel             =>        Write_Fiq_Sel,
       Read_TxPkt_Lngth          =>        Read_TxPkt_Lngth,
       Wr_data                   =>        Wr_data
      );

end STR;