usb_new_pvci_eng_str.vhdl

实现USB接口功能的VHDL和verilog完整源代码

       Write_Intr_Set:         in  one_bit;          -- Write interrupt set register
       Write_TxPkt_Lngth:      in  one_bit;          -- Write Tx packet length register
       Write_Usb_Cntrl:        in  one_bit;          -- Write USB control register
       Read_Usb_Cntrl:         in  one_bit;          -- Read USB control register
       Read_Cmd_Data:          in  one_bit;          -- Read command data
       Read_Receive_Data:      in  one_bit;          -- Read receive data
       Read_Intr_Status:       in  one_bit;          -- Read interrupt status register
       Read_Intr_enable:       in  one_bit;          -- Read interrupt enable register
       Read_RxPkt_Lngth:       in  one_bit;          -- Read rx packet length register
       Read_TxPkt_Lngth:       in  one_bit;          -- Read Tx packet length register
       Wr_Data:                in  four_bytes;       -- Write data
       Rd_Data:                out four_bytes;       -- Read data
       Error:                  in  one_bit;          -- Error
       Write_Fiq_Sel:          in  one_bit;          -- Write Fiq sel register

       -- Interface to RCV_RAM

       DataFromRam:            in  four_bytes;       -- Data from Recieve RAM
       RxRam_Read:             out one_bit;          -- Receive RAM read
       Rx_Pkt_End:             out one_bit;          -- Rx packet read end
       Endpoint_Nr:            out logical_ep_type;  -- Logical endpoint number
       write_pkt_length:       in  boolean;          -- Write packet length

       -- Interface to TRNSMT_RAM

       TxRam_write:            out one_bit;          -- Receive RAM write
       DataToRam:              out four_bytes;       -- Data to Receive RAM
       Tx_Pkt_End:             out one_bit;          -- Tx packet write end 
       Packet_Length:          out ten_bits;         -- Number of bytes for IN packet 

       -- Interface to SYNCHRONIZER module

       CommandDataChannel:     in  byte;             -- Command data
       CmdDataValid_Out:       in  boolean;          -- Command data valid           
       CmdAccept_Out:          in  boolean;          -- Command code accepted
       CommandCode:            out eleven_bits;      -- Command code
       CmdCodeValid:           out boolean;          -- Command code valid
       EndTransfer_Cmd_D:      in  one_bit;          -- End of command data transfer
       USBEp0IntrSet:          in  one_bit;          -- USB Ep0 interrupt
       USBEp1IntrSet:          in  one_bit;          -- USB Ep1 interrupt
       USBEp2IntrSet:          in  one_bit;          -- USB Ep2 interrupt
       USBEp3IntrSet:          in  one_bit;          -- USB Ep3 interrupt
       USBEp4IntrSet:          in  one_bit;          -- USB Ep4 interrupt
       USBEp5IntrSet:          in  one_bit;          -- USB Ep5 interrupt
       USBEp6IntrSet:          in  one_bit;          -- USB Ep6 interrupt
       USBEp7IntrSet:          in  one_bit;          -- USB Ep7 interrupt
       USBDevIntrSet:          in  one_bit;          -- USB Dev interrupt       
       FrameIntr_Set:          in  one_bit;          -- Frame interrupt
       USBToggleBuffer_Out:    in  T_toggleArray;
       FullBuffer_EP:          in  T_Full;

       -- Interrupt signals

       Intr_Request_Irq:       out one_bit;          -- All Interrupt request to processor
       Intr_Request_Fiq:       out one_bit;          -- Frame Interrupt request to processor
       
       -- Clock and reset from system

       pvci_reset_n:           in  one_bit;
       clk:                    in  one_bit
      );
end component;

component PVCI_CNTRL
  port(
       -- Interface to APB_WRAPPER module
                     
       clk:                 in   one_bit;          -- PVCI clock
       pvci_reset_n:        in   one_bit;          -- Reset
       req:                 in   one_bit;          -- Request
       address:             in   byte;             -- Address
       rnw:                 in   one_bit;          -- '0' write, '1' read
       w_data:              in   four_bytes;       -- Write data
       gnt:                 out  one_bit;          -- Grant
       r_data:              out  four_bytes;       -- Read data
       error:               out  one_bit;          -- Error 
       
       -- Interface to USB_CONTROLLER module
       
       Rd_data:             in   four_bytes;       -- Data from PVCI
       Write_Cmd_Code:      out  one_bit;          -- Write command code
       Read_Cmd_Data:       out  one_bit;          -- Read command data
       Read_Receive_Data:   out  one_bit;          -- Read recive data
       Write_Transmt_Data:  out  one_bit;          -- Write transmit data
       Write_USB_Cntrl:     out  one_bit;          -- Write USB control register
       Read_USB_Cntrl:      out  one_bit;          -- Read USB control register
       Read_RxPkt_Lngth :   out  one_bit;          -- Read Rx packet length
       Write_TxPkt_Lngth:   out  one_bit;          -- Write Tx packet length
       Read_Intr_Status:    out  one_bit;          -- Read interrupt status register
       Read_Intr_enable:    out  one_bit;          -- Read interrupt enable register
       Write_Intr_Enable:   out  one_bit;          -- Write interrupt enable register
       Write_Intr_Clear:    out  one_bit;          -- Write interrupt clear register
       Write_Intr_Set :     out  one_bit;          -- Write interrupt set register
       Read_TxPkt_Lngth:    out  one_bit;          -- Read Tx packet length
       Wr_data:             out  four_bytes;       -- Data to PVCI
       Write_Fiq_Sel:       out  one_bit           -- Write Fiq Sel register
      );
 end component; 

-- signals declarations

signal CommandCode:             eleven_bits;          -- Command code
signal CmdCodeValid:            boolean;              -- Command code valid
signal CmdAccept_Out:           boolean;              -- Command code accepted
signal CommandDataChannel:      byte;                 -- Command data
signal CmdDataValid_Out:        boolean;              -- Command data valid
signal USBEp0IntrSet:           one_bit;              -- USB Ep0 interrupt 
signal USBEp1IntrSet:           one_bit;              -- USB Ep1 interrupt 
signal USBEp2IntrSet:           one_bit;              -- USB Ep2 interrupt 
signal USBEp3IntrSet:           one_bit;              -- USB Ep3 interrupt 
signal USBEp4IntrSet:           one_bit;              -- USB Ep4 interrupt 
signal USBEp5IntrSet:           one_bit;              -- USB Ep5 interrupt 
signal USBEp6IntrSet:           one_bit;              -- USB Ep6 interrupt 
signal USBEp7IntrSet:           one_bit;              -- USB Ep7 interrupt 
signal USBDevIntrSet:           one_bit;              -- USB Dev interrupt 
signal FrameIntr_Set:           one_bit;              -- Frame interrupt
signal EndTransfer_Cmd_D:       one_bit;              -- End of transfer for command data
signal RxDataAccepted:          boolean;              -- Handshake: OUT EP data accepted 
signal RxCore_Data:             byte;                 -- Data for OUT endpoints
signal EP_number_Out:           Int_EndPointType;     -- Physical endpoint number
signal End_Transfer_D:          one_bit;              -- End of transfer for endpoint data
signal RxError_Out:             boolean;              -- Error in data packet
signal USBToggleBuffer_Out:     T_ToggleArray;        -- USB buffer toggle
signal UCToggleBuffer_Out:      T_ToggleArray;        -- UC buffer toggle
signal FullBuffer_EP:           T_Full;               -- Buffer full for endpoints
signal PI_IsoToggle_Out:        integer range 0 to 1; -- ISO buffer toggle
signal Read_Data:               one_bit;              -- Read data from RAM
signal start_in_tx:             one_bit;              -- Start of IN transfer
signal TxDest_Endp:             Int_EndPointType;     -- Physical endpoint number of IN
signal DataFromRam:             four_bytes;            -- Data read from RAM
signal RxRam_Read:              one_bit;               -- RAM read
signal Rx_Pkt_End:              one_bit;               -- End of packet read
signal Packet_Length:           ten_bits;              -- Number of bytes for IN packet
signal TxRam_Write:             one_bit;               -- Write into RAM
signal EndPoint_Nr:             logical_ep_type;       -- Logical endpoint number
signal DataToRam:               four_bytes;            -- Data word to RAM
signal Tx_Pkt_End:              one_bit;               -- End of packet is reached
signal Write_Cmd_Code:          one_bit;          -- Write command register
signal Write_Transmt_Data:      one_bit;          -- Write transmit data register
signal Write_Intr_Enable:       one_bit;          -- Write interrupt enable register
signal Write_Intr_Clear:        one_bit;          -- Write interrupt clear register
signal Write_Intr_Set:          one_bit;          -- Write interrupt set register
signal Write_TxPkt_Lngth:       one_bit;          -- Write Tx packet length register
signal Write_Usb_Cntrl:         one_bit;          -- Write USB control register
signal Read_Usb_Cntrl:          one_bit;          -- Read USB control register
signal Read_Cmd_Data:           one_bit;          -- Read command data
signal Read_Receive_Data:       one_bit;          -- Read receive data
signal Read_Intr_Status:        one_bit;          -- Read interrupt status register
signal Read_Intr_enable:        one_bit;          -- Read interrupt enable register
signal Read_RxPkt_Lngth:        one_bit;          -- Read rx packet length register
signal Wr_Data:                 four_bytes;       -- Write data
signal Rd_Data:                 four_bytes;       -- Read data
signal if_busy_i:               boolean;
signal write_pkt_length:        boolean;          -- Write packet length
signal Error_int:               one_bit;          -- Error
signal Read_TxPkt_Lngth:        one_bit;          -- Read Tx packet length register
signal Write_Fiq_Sel:           one_bit;          -- Write Fiq sel register

begin
   
   if_busy  <=  if_busy_i; -- if_busy is a output port as well as it has to be connected 
                           -- to a internal module  
   Error    <= Error_int;
 
   SYNCHRONIZER_1: SYNCHRONIZER 
   port map
      (
       Trans_Enable              =>          Trans_Enable,
       Read                      =>          Read,
       EP_number                 =>          EP_number,
       Data_Out                  =>          Data_Out,
       End_Transfer              =>          End_Transfer,
       EndTransfer_Cmd           =>          EndTransfer_Cmd,
       USBEp0Intr_Set            =>          USBEp0Intr_Set,
       USBEp1Intr_Set            =>          USBEp1Intr_Set,
       USBEp2Intr_Set            =>          USBEp2Intr_Set,
       USBEp3Intr_Set            =>          USBEp3Intr_Set,
       USBEp4Intr_Set            =>          USBEp4Intr_Set,
       USBEp5Intr_Set            =>          USBEp5Intr_Set,
       USBEp6Intr_Set            =>          USBEp6Intr_Set,
       USBEp7Intr_Set            =>          USBEp7Intr_Set,
       USBDevIntr_Set            =>          USBDevIntr_Set,
       USBToggleBuffer           =>          USBToggleBuffer,
       UCToggleBuffer            =>          UCToggleBuffer,
       FullBuffer_UC             =>          FullBuffer_UC,
       PI_IsoToggle              =>          PI_IsoToggle,
       RxError                   =>          RxError,
       reg_ram_read              =>          reg_ram_read,
       reg_ram_tag               =>          reg_ram_tag,
       CommandData               =>          CommandData,
       CmdDataValid              =>          CmdDataValid,
       CmdAccept                 =>          CmdAccept,
       CommandCodeChannel        =>          CommandCodeChannel,
       CmdCodeValid_Out          =>          CmdCodeValid_Out,
       If_Busy                   =>          If_Busy_i,

       -- Interface to USB_CNTRL

       CommandCode               =>          CommandCode,
       CmdCodeValid              =>          CmdCodeValid,
       CmdAccept_Out             =>          CmdAccept_Out,
       CommandDataChannel        =>          CommandDataChannel,
       CmdDataValid_Out          =>          CmdDataValid_Out,
       USBEp0IntrSet             =>          USBEp0IntrSet,
       USBEp1IntrSet             =>          USBEp1IntrSet,
       USBEp2IntrSet             =>          USBEp2IntrSet,
       USBEp3IntrSet             =>          USBEp3IntrSet,
       USBEp4IntrSet             =>          USBEp4IntrSet,
       USBEp5IntrSet             =>          USBEp5IntrSet,
       USBEp6IntrSet             =>          USBEp6IntrSet,
       USBEp7IntrSet             =>          USBEp7IntrSet,
       USBDevIntrSet             =>          USBDevIntrSet,       
       FrameIntr_Set             =>          FrameIntr_Set,
       EndTransfer_Cmd_D         =>          EndTransfer_Cmd_D,

       -- Interface to RCV_RAM