usb_new_pvci_eng_str.vhdl

实现USB接口功能的VHDL和verilog完整源代码

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--
--  P H I L I P S  C O M P A N Y  R E S T R I C T E D
--                                         
--  Copyright (c) 1998.                    
--
--  Philips Electronics N.V.
--
--  Philips Semiconductors
--  Interconnectivity and Processor Peripheral group
--  Bangalore,India
--  All rights reserved. Reproduction in whole or in part is prohibited
--  without the written permission of the copyright owner.
--
--------------------------------------------------------------------------------
--
--  File            : usb_new_pvci_eng_str.vhdl 
--
--  Module          : PVCI_ENG_STR 
--
--  Project         : VPB bus Interface to USB 1.1 Device(USBFS22)
--
--  Author          :              
--
--  Description     : The architecture of PVCI_ENG_STR block
--
--  Status          : 
--
--  Contact address : 
--
--------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

library work;
use work.PCK_GENERAL.all;
use work.PCK_HANDLERS.all;
use work.PCK_CONFIGURATION.all;

library work;
use work.PCK_APB.all;

library work;
use work.all;

architecture STR of PVCI_ENG is

component SYNCHRONIZER 
  port(
       -- Interface to EP_HANDLER modlue

       Trans_Enable:          in   one_bit;              -- Data transfer enable
       Read:                  in   one_bit;              -- '1' read data
       EP_number:             in   Int_EndPointType;     -- Physical endpoint number
       Data_Out:              in   byte;                 -- Data bus for OUT endpoints
       End_Transfer:          in   one_bit;              -- End of transfer for packet data 
       EndTransfer_Cmd:       in   one_bit;              -- End of transfer for command data
       USBEp0Intr_Set:        in   one_bit;              -- USB Ep0 interrupt
       USBEp1Intr_Set:        in   one_bit;              -- USB Ep1 interrupt
       USBEp2Intr_Set:        in   one_bit;              -- USB Ep2 interrupt
       USBEp3Intr_Set:        in   one_bit;              -- USB Ep3 interrupt
       USBEp4Intr_Set:        in   one_bit;              -- USB Ep4 interrupt
       USBEp5Intr_Set:        in   one_bit;              -- USB Ep5 interrupt
       USBEp6Intr_Set:        in   one_bit;              -- USB Ep6 interrupt
       USBEp7Intr_Set:        in   one_bit;              -- USB Ep7 interrupt
       USBDevIntr_Set:        in   one_bit;              -- USB Dev interrupt       
       USBToggleBuffer:       in   T_ToggleArray;        -- USB buffer toggle 
       UCToggleBuffer:        in   T_ToggleArray;        -- UC buffer toggle
       FullBuffer_UC:         in   T_Full;               -- Buffer full for endpoints
       PI_IsoToggle:          in   integer range 0 to 1; -- ISO buffer toggle
       RxError:               in   boolean;              -- Error in packet transfer
       reg_ram_read:          in   one_bit;              -- Start of IN transfer
       reg_ram_tag:           in   Int_EndPointType;     -- Physical endpoint number
       CommandData:           in   byte;                 -- Command data
       CmdDataValid:          in   boolean;              -- Command data valid
       CmdAccept:             in   boolean;              -- Handshake signal for Command accepted
       CommandCodeChannel:    out  eleven_bits;          -- Command code
       CmdCodeValid_Out:      out  boolean;              -- Command code valid
       If_Busy:               out  boolean;              -- Interface busy
       
       -- Interface to USB_CNTRL module

       CommandCode:           in   eleven_bits;          -- Command code
       CmdCodeValid:          in   boolean;              -- Command code valid
       CmdAccept_Out:         out  boolean;              -- Command code accepted
       CommandDataChannel:    out  byte;                 -- Command data
       CmdDataValid_Out:      out  boolean;              -- Command data valid
       USBEp0IntrSet:         out  one_bit;              -- USB Ep0 interrupt
       USBEp1IntrSet:         out  one_bit;              -- USB Ep1 interrupt
       USBEp2IntrSet:         out  one_bit;              -- USB Ep2 interrupt
       USBEp3IntrSet:         out  one_bit;              -- USB Ep3 interrupt
       USBEp4IntrSet:         out  one_bit;              -- USB Ep4 interrupt
       USBEp5IntrSet:         out  one_bit;              -- USB Ep5 interrupt
       USBEp6IntrSet:         out  one_bit;              -- USB Ep6 interrupt
       USBEp7IntrSet:         out  one_bit;              -- USB Ep7 interrupt
       USBDevIntrSet:         out  one_bit;              -- USB Dev interrupt        
       FrameIntr_Set:         out  one_bit;              -- Frame interrupt
       EndTransfer_Cmd_D:     out  one_bit;              -- End of transfer for command data

       -- Interface to RCV_RAM module
       
       RxDataAccepted:        in   boolean;              -- Handshake: OUT EP data accepted 
       RxCore_Data:           out  byte;                 -- Data for OUT endpoints
       EP_number_Out:         out  Int_EndPointType;     -- Physical endpoint number
       End_Transfer_D:        out  one_bit;              -- End of transfer for endpoint data
       RxError_Out:           out  boolean;              -- Error in data packet
       USBToggleBuffer_Out:   out  T_ToggleArray;        -- USB buffer toggle
       UCToggleBuffer_Out:    out  T_ToggleArray;        -- UC buffer toggle
       FullBuffer_EP:         out  T_Full;               -- Buffer full for endpoints
       PI_IsoToggle_Out:      out  integer range 0 to 1; -- ISO buffer toggle
       
       -- Interface to TRNSMT_RAM module 
       
       Read_Data:             out  one_bit;              -- Read data from RAM
       start_in_tx:           out  one_bit;              -- Start of IN transfer
       TxDest_Endp:           out  Int_EndPointType;     -- Physical endpoint number of IN
       
       -- Clock and Reset from system 
       
       clk:                   in   one_bit;              -- APB bus clock
       pvci_reset_n:          in   one_bit               -- APB bus Reset
      );
end component;

component RCV_RAM
  port(
       -- Interface to SYNCHRONIZER module

       If_Busy:             in    boolean;               -- Data available in rcv_transmt.
       RxCore_Data:         in    byte;                  -- The Data to be transferred.
       EP_number_out:       in    Int_EndPointType;      -- Physical endpoint number
       Rx_N_data:           in    integer range 0 to MAX_OVERFLOW_SIZE; -- Packet size
       End_Transfer_D:      in    one_bit;               -- End of transfer for packet data
       RxError_Out:         in    boolean;               -- Error in data packet transfer
       FullBuffer_EP:       in    T_Full;                -- Full buffer for endpoints
       USBToggleBuffer_Out: in    T_ToggleArray;         -- USB toggle buffer
       UCToggleBuffer_Out:  in    T_ToggleArray;         -- UC Toggle buffer
       PI_IsoToggle_Out:    in    integer range 0 to 1;  -- ISO toggle buffer
       RxDataAccepted:      out   boolean;               -- Data accepted
       
       -- Interface to RAM module

       RxRAM_DQ_In:         in    four_bytes;            -- RAM data in-bus (32-bits)
       RxRAM_E_N:           out   one_bit;               -- RAM enable, active low
       RxRAM_W_N:           out   one_bit;               -- RAM write, active low
       RxRAM_G_N:           out   one_bit;               -- RAM grant(read), active low
       RxRAM_A:             out   RxRAMAddr_bits;        -- RAM address bus (??-bits)
       RxRAM_DQ_Out:        out   four_bytes;            -- RAM data out-bus(32-bits)

       -- Interface to USB_CONTROLLER module
       DataFromRam:         out   four_bytes;            -- Data read from RAM
       RxRam_Read:          in    one_bit;               -- RAM read
       Rx_Pkt_End:          in    one_bit;               -- End of packet read
       Endpoint_Nr:         in    logical_ep_type;       -- Logical endpoint
       write_pkt_length:    out   boolean;               -- Write packet length
       
       -- Clock and reset from system

       clk:                 in    one_bit;               -- APB bus clock
       pvci_reset_n:        in    one_bit                -- APB bus Reset
      );
end component;

component TRNSMT_RAM
  port(
       -- Interface to SYNCHRONIZER module

       UCToggleBuffer_Out:  in    T_ToggleArray;           -- UC toggle buffer
       USBToggleBuffer_Out: in    T_ToggleArray;           -- USB toggle buffer
       FullBuffer_EP:       in    T_Full;                  -- Full buffer for all endpoints
       PI_IsoToggle_Out:    in    integer range 0 to 1;    -- ISO toggle buffer
       start_in_tx:         in    one_bit;                 -- Start of IN transfer
       TxDest_Endp:         in    Int_EndPointType;        -- Physical endpoint number
       Read_Data:           in    one_bit;                 -- Read data
       End_Transfer_D:      in    one_bit;                 -- End of packet data transfer

       -- Interface to EP_HANDLER module

       Read_Req:            out   one_bit;                 -- ????
       Data_In:             out   byte;                    -- Data bus for IN data
       TxDest_NData:        out   nine_bits;               -- Number of bytes for IN packet

       -- Interface to USB_CONTROLLER module

       Packet_Length:       in    ten_bits;                -- Number of bytes for IN packet
       TxRam_Write:         in    one_bit;                 -- Write into RAM
       EndPoint_Nr:         in    logical_ep_type;         -- Logical endpoint number
       DataToRam:           in    four_bytes;              -- Data word to RAM
       Tx_Pkt_End:          in    one_bit;                 -- End of packet is reached

       -- Interface to TRNSMT_RAM module

       TxRAM_E_N:           out   one_bit;                 -- RAM enable, active low
       TxRAM_W_N:           out   one_bit;                 -- RAM write, active low
       TxRAM_G_N:           out   one_bit;                 -- RAM grant(read), active low
       TxRAM_A:             out   TxRAMAddr_bits;          -- RAM address bus
       TxRAM_DQ_In:         in    four_bytes;              -- RAM data in-bus
       TxRAM_DQ_Out:        out   four_bytes;              -- RAM data out-bus
       
       -- Clock and reset from system

       clk:                 in    one_bit;                 -- APB bus clock
       pvci_reset_n:        in    one_bit                  -- APB bus reset
      );
end component;

component USB_CNTRL
  port(
       -- Interface to PVCI_CONTROLLER

       Write_Cmd_Code:         in  one_bit;          -- Write command register
       Write_Transmt_Data:     in  one_bit;          -- Write transmit data register
       Write_Intr_Enable:      in  one_bit;          -- Write interrupt enable register
       Write_Intr_Clear:       in  one_bit;          -- Write interrupt clear register