usb_new_usbvpb_top_str.vhdl

实现USB接口功能的VHDL和verilog完整源代码

          scanclock     : in  std_logic;  -- Scan Clock
          tck           : in  std_logic;  -- Test Clock
          chb           : in  std_logic_vector(15 downto 0);  -- Client Host Bus
          tdi           : in  std_logic;  -- Test Data Input
          tdo           : out std_logic  -- Test Data Output
	);
end component;

signal   USB_RxRAM_E_N: 	std_logic;
signal   USB_RxRAM_W_N: 	std_logic;  
signal   USB_RxRAM_G_N: 	std_logic;
signal   USB_RxRAM_A:		std_logic_vector(6 downto 0); 
signal   USB_RxRAM_DQ_In:	std_logic_vector(31 downto 0);
signal   USB_RxRAM_DQ_out:	std_logic_vector(31 downto 0);
signal   USB_TxRAM_E_N: 	std_logic;
signal   USB_TxRAM_W_N: 	std_logic;
signal   USB_TxRAM_G_N: 	std_logic;
signal   USB_TxRAM_A:		std_logic_vector(6 downto 0); 
signal   USB_TxRAM_DQ_In:	std_logic_vector(31 downto 0);
signal   USB_TxRAM_DQ_out:	std_logic_vector(31 downto 0);
signal   CL:			std_logic;
signal   r_data:		std_logic_vector(31 downto 0);  	   
signal   gnt:			std_logic;		    
signal   pvci_reset_n:  	std_logic;		    
signal   req:			std_logic;		   
signal   address:		std_logic_vector(7 downto 0);		   
signal   rnw:			std_logic;		   
signal   w_data:		std_logic_vector(31 downto 0); 
signal   error:                 std_logic; 		   
signal   chb    : 		std_logic_vector(15 downto 0);
signal   USB_RxRAM_WE:		std_logic;
signal   USB_TxRAM_WE:		std_logic;
begin
	USB_RxRAM_WE <= not(USB_RxRAM_W_N);
	USB_TxRAM_WE <= not(USB_TxRAM_W_N);
 USBPVCI_dft_1 : USBPVCI_dft
    port map(
             -- Clocks
             USB_MainClk        => USB_MainClk,
	     USB_BitClk         => USB_BitClk,
	     USB_BitClk_Out     => USB_BitClk_Out,

             -- Connect
             USB_Connect_N      => USB_Connect_N,
             
             -- Power
             USB_VBus           => USB_VBus,
             
             -- Test mode signals
             USB_TestMode       =>  USB_TestMode,
             USB_Test_Resetn    => USB_Test_Resetn,
             
             -- Rx Raminterface
             USB_RxRAM_E_N      => USB_RxRAM_E_N,
             USB_RxRAM_W_N      => USB_RxRAM_W_N,         
             USB_RxRAM_G_N      => USB_RxRAM_G_N,
             USB_RxRAM_A        => USB_RxRAM_A,
             USB_RxRAM_DQ_In    => USB_RxRAM_DQ_In,
             USB_RxRAM_DQ_out   => USB_RxRAM_DQ_out,
             
             -- Tx Raminterface
             USB_TxRAM_E_N      => USB_TxRAM_E_N,
             USB_TxRAM_W_N      => USB_TxRAM_W_N,
             USB_TxRAM_G_N      => USB_TxRAM_G_N,
             USB_TxRAM_A        => USB_TxRAM_A,
             USB_TxRAM_DQ_In    => USB_TxRAM_DQ_In,
             USB_TxRAM_DQ_out   => USB_TxRAM_DQ_out,
             
             -- Suspend
             USB_Suspend        => USB_Suspend,
             
             -- pvci interface
             r_data             => r_data,
             gnt                => gnt,
             clk                => PCLK,
             pvci_reset_n       => pvci_reset_n,
             req                => req,
             address            => address,
             rnw                => rnw,
             w_data             => w_data,
             error              => error,
             
             -- interrupt request
             USB_Int_Req_Irq    => USB_Int_Req_Irq,
             USB_Int_Req_Fiq    => USB_Int_Req_Fiq,
                          
             -- Upstream port
             USB_UP_LED_N       => USB_UP_LED_N,
             USB_UP_RxDM        => USB_UP_RxDM,
             USB_UP_RxDP        => USB_UP_RxDP,
             USB_UP_RxRCV       => USB_UP_RxRCV,
             USB_UP_TxDM        => USB_UP_TxDM,
             USB_UP_TxDP        => USB_UP_TxDP,
             USB_UP_TxEnable_N  => USB_UP_TxEnable_N,
             USB_NeedClk        => USB_NeedClk
            );

 VPB_WRAPPER_1 : VPB_WRAPPER
    port map(
             -- Interface to VPB bus
             PSEL               => PSEL,
             PENABLE            => PENABLE,
             PADDR              => PADDR, 
             PWRITE             => PWRITE,
             PRESETn            => PRESETn,
             PCLK               => PCLK,
             PWDATA             => PWDATA,
             PRDATA             => PRDATA,
             PRDY               => PRDY,
             
        
             -- Interface to PVCI_CNTRL module
             r_data             => r_data,                    
             gnt                => gnt,                      
             pvci_reset_n       => pvci_reset_n,                 
             req                => req,           
             address            => address,      
             rnw                => rnw,  
             w_data             => w_data,
             error              => error
             );           
          
RXRAM_1: vsc9_ram_cm0 
   port map(
   	  sys_ck0       => CL,  	-- System Memory Address Strobe
          sys_en0       => USB_RxRAM_E_N,  -- System Memory Block Select
          sys_we0       => USB_RxRAM_WE,  -- System Memory Write Enable
          sys_ad0       => USB_RxRAM_A,  -- System Memory Address Bus
          sys_di0       => USB_RxRAM_DQ_out,  -- System Memory Data Input
          sys_do0       => USB_RxRAM_DQ_In,  -- System Memory Data Output
          scantestmode  => scan_test,  	-- Scan Test Mode
          scanclock     => scanclock, 	-- Scan Clock
          tck           => tck,  	-- Test Clock
          tdi          =>   tdi(0),    	-- Test Data Input
          tdo          =>   tdo(0),  	-- Test Data Output
          chb           => chb
           );

TXRAM_1: vsc9_ram_cm1
   port map(
   	  sys_ck0       => CL,  	-- System Memory Address Strobe
          sys_en0       => USB_TxRAM_E_N,  -- System Memory Block Select
          sys_we0       => USB_TxRAM_WE,  -- System Memory Write Enable
          sys_ad0       => USB_TxRAM_A,  -- System Memory Address Bus
          sys_di0       => USB_TxRAM_DQ_out,  -- System Memory Data Input
          sys_do0       => USB_TxRAM_DQ_In,  -- System Memory Data Output
          scantestmode  => scan_test,  	-- Scan Test Mode
          scanclock     => scanclock, 	-- Scan Clock
          tck           => tck,  	-- Test Clock
          tdi          =>   tdi(1),    	-- Test Data Input
          tdo          =>   tdo(1),  	-- Test Data Output
          chb           => chb
          );
          
BIST_HOST: vsc9_ram
  port map(
          tck           => tck,  
          ntrst         => ntrst, 	-- Test Reset (active low)
          tbe           => tbe,  	-- Test BIST Enable
          trunbist      => trunbist,  	-- Test BIST Run/hold
          tend          =>  tend,    	-- Test End
          dri           =>  dri,      	-- Data Retention Input (global data retention ready)
          dro           =>  dro,      	-- Data Retention Output (local data retention ready)
          tdi          =>   tdi(2),    	-- Test Data Input
          tdo          =>   tdo(2),  	-- Test Data Output
          tseir        =>   tseir,	-- Debug Scan Enable Instruction Register
          tsedr        =>   tsedr,	-- Debug Scan Enable Data Register
          chb           => chb
          );



CL <= PCLK NOR se;
                
END str;