usb_new_usbvpb_top_str.vhdl

实现USB接口功能的VHDL和verilog完整源代码

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--
--  P H I L I P S  C O M P A N Y  R E S T R I C T E D
--                                         
--  Copyright (c) 1998.                    
--
--  Philips Electronics N.V.
--
--  Philips Semiconductors
--  Interconnectivity and Processor Peripheral group
--  Bangalore,India
--  All rights reserved. Reproduction in whole or in part is prohibited
--  without the written permission of the copyright owner.
--
--------------------------------------------------------------------------------
--
--  File            : usb_new_usbvpb_top_str.vhdl 
--
--  Module          : USBVPB_TOP
--
--  Project         : VPB bus Interface to USB 1.1 Device(USBFS22)
--
--  Author          :              
--
--  Description     : The architecture of USBVPB_TOP block
--
--  Modules instantiated : USBPVCI_DfT, 
--                         VPB_WRAPPER,
--                         RAM_DfT.
--                       
--  Status          : 
--
--  Contact address : 
--
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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

library work;
use work.all;

ARCHITECTURE str OF USBVPB_TOP IS

 component USBPVCI_DfT 
    port(
          -- Clocks
          USB_MainClk:          in    std_logic;                     -- Main clock
          USB_NeedClk:          out   std_logic;                     -- Device needs clock
	  USB_BitClk:           in    std_logic;                     -- Bit clock in
	  USB_BitClk_Out:       out   std_logic;                     -- Bit clock out

          -- Connect
          USB_Connect_N:        out   std_logic;                     -- Controls switch for 
                                                                     -- softconnect
          -- Power
          USB_VBus:             in    std_logic;                     -- Bus power is present

          -- Test mode signals
          USB_TestMode:         in    std_logic;                     -- Select test mode
          USB_Test_Resetn:      in    std_logic;                     -- Resetn during test mode

          -- Rx Raminterface
          USB_RxRAM_E_N:        out   std_logic;                     -- RxRAM enable
          USB_RxRAM_W_N:        out   std_logic;                     -- RxRAM write
          USB_RxRAM_G_N:        out   std_logic;                     -- RxRAM grant
          USB_RxRAM_A:          out   std_logic_vector(6 downto 0);  -- RxRAM address 
          USB_RxRAM_DQ_In:      in    std_logic_vector(31 downto 0); -- RxRAM out data
          USB_RxRAM_DQ_Out:     out   std_logic_vector(31 downto 0); -- RxRAM in data

          -- Tx Raminterface
          USB_TxRAM_E_N:        out   std_logic;                     -- TxRAM enable
          USB_TxRAM_W_N:        out   std_logic;                     -- TxRAM write
          USB_TxRAM_G_N:        out   std_logic;                     -- TxRAM grant
          USB_TxRAM_A:          out   std_logic_vector(6 downto 0);  -- TxRAM address 
          USB_TxRAM_DQ_In:      in    std_logic_vector(31 downto 0); -- TxRAM out data
          USB_TxRAM_DQ_Out:     out   std_logic_vector(31 downto 0); -- TxRAM in data

          -- Suspend
          USB_Suspend:          out std_logic;                     -- Device Suspend
          
          -- Interrupt request
          USB_Int_Req_Irq:      out   std_logic;                     -- IRQ interrupt
          USB_Int_Req_Fiq:      out   std_logic;                     -- FIQ interrupt
          
          -- Interface to PVCI
          r_data:               out   std_logic_vector(31 downto 0); -- read data
          gnt:                  out   std_logic;                     -- grant
          clk:                  in    std_logic;                     -- clock
          pvci_reset_n:         in    std_logic;                     -- reset
          req:                  in    std_logic;                     -- request
          address:              in    std_logic_vector(7 downto 0);  -- address
          rnw:                  in    std_logic;                     -- read/write
          w_data:               in    std_logic_vector(31 downto 0); -- write data
          error:                out   std_logic;                     -- error
                    
          -- Upstream port
          USB_UP_LED_N:         out   std_logic;                     -- LED
          USB_UP_RxDM:          in    std_logic;                     -- Rx D-
          USB_UP_RxDP:          in    std_logic;                     -- Rx D+
          USB_UP_RxRCV:         in    std_logic;                     -- Rx RCV
          USB_UP_TxDM:          out   std_logic;                     -- Tx D-
          USB_UP_TxDP:          out   std_logic;                     -- Tx D+
          USB_UP_TxEnable_N:    out   std_logic                     -- Tx Enable
          );
 end component;


 component VPB_WRAPPER
    port(
         -- Interface to VPB bus

         PSEL:                  in    std_logic;                     -- USB select
         PENABLE:               in    std_logic;                     -- USB enable
         PADDR:                 in    std_logic_vector(7 downto 0);  -- USB addres
         PWRITE:                in    std_logic;                     -- '1' write, '0' read
         PRESETn:               in    std_logic;                     -- Reset
         PCLK:                  in    std_logic;                     -- CLock
         PWDATA:                in    std_logic_vector(31 downto 0); -- Write data
         PRDATA:                out   std_logic_vector(31 downto 0); -- Read data
         PRDY:                  out   std_logic;                     -- Ready
         -- Interface to PVCI_CNTRL module

         r_data:                in    std_logic_vector(31 downto 0); -- read data
         gnt:                   in    std_logic;                     -- Grant
         pvci_reset_n:          out   std_logic;                     -- PVCI reset
         req:                   out   std_logic;                     -- Request
         address:               out   std_logic_vector(7 downto 0);  -- Address
         rnw:                   out   std_logic;                     -- '0' write, '1' read
         w_data:                out   std_logic_vector(31 downto 0); -- PVCI Write data
         error:                 in    std_logic                     -- error

        );
 end component;    


component vsc9_ram 
   port ( tck       : in  std_logic;  -- Test Clock
          ntrst     : in  std_logic;  -- Test Reset (active low)
          tbe       : in  std_logic;  -- Test BIST Enable
          trunbist  : in  std_logic;  -- Test BIST Run/hold
          tend      : out std_logic;  -- Test End
          dri       : in  std_logic;  -- Data Retention Input (global data retention ready)
          dro       : out std_logic;   -- Data Retention Output (local data retention ready)
          tseir     : in  std_logic;  -- Debug Scan Enable Instruction Register
          tsedr     : in  std_logic;  -- Debug Scan Enable Data Register
          tdi       : in  std_logic;  -- Test Data Input
          tdo       : out std_logic;  -- Test Data Output
          chb       : out std_logic_vector(15 downto 0)  -- Client Host Bus
	);
end component;

component vsc9_ram_cm0 
   port ( sys_ck0       : in  std_logic;  -- System Memory Address Strobe
          sys_en0       : in  std_logic;  -- System Memory Block Select
          sys_we0       : in  std_logic;  -- System Memory Write Enable
          sys_ad0       : in  std_logic_vector(6 downto 0);  -- System Memory Address Bus
          sys_di0       : in  std_logic_vector(31 downto 0);  -- System Memory Data Input
          sys_do0       : out std_logic_vector(31 downto 0);  -- System Memory Data Output
          scantestmode  : in  std_logic;  -- Scan Test Mode
          scanclock     : in  std_logic;  -- Scan Clock
          tck           : in  std_logic;  -- Test Clock
          chb           : in  std_logic_vector(15 downto 0);  -- Client Host Bus
          tdi           : in  std_logic;  -- Test Data Input
          tdo           : out std_logic  -- Test Data Output
          ); 
end component;

component vsc9_ram_cm1 
   port ( sys_ck0       : in  std_logic;  -- System Memory Address Strobe
          sys_en0       : in  std_logic;  -- System Memory Block Select
          sys_we0       : in  std_logic;  -- System Memory Write Enable
          sys_ad0       : in  std_logic_vector(6 downto 0);  -- System Memory Address Bus
          sys_di0       : in  std_logic_vector(31 downto 0);  -- System Memory Data Input
          sys_do0       : out std_logic_vector(31 downto 0);  -- System Memory Data Output
          scantestmode  : in  std_logic;  -- Scan Test Mode