hdli.vhd

实现USB接口功能的VHDL和verilog完整源代码

--------------------------------------------------------------------------------
--
-- Package for use with HDLi RTL code
--
--
-- Created 9/10/95 VLSI Technology Inc.
--
-- Functions defined in this package have been verified in the supported
-- HDL synthesizers to parse without errors.  Some of the functions can
-- be rewritten to produce faster simulations but at the expense of problems
-- when parsed in a HDL synthesizer.  The simulation improvements have been
-- analyzed and the gains were proven to be minor.
--
-- 11/04/98   Changed all "*extend" functions to use an alias for the
--            parameter.  This allows vectors of the type (m downto n)
--            where n is not zero.
-- 04/28/98   Added HDLi_Reduce_And
-- 04/14/97   Added HDLi_SUmult 
-- 02/12/96   Changed HDLi_Smult to return A'length + B'length bits
-- 09/10/96   Added compare routines
--
--------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.all;

package HDLI is
        
    function HDLi_Reduce_Xor (INPUT: Std_Logic_Vector) return Std_Logic;
    function HDLi_Reduce_And (INPUT: Std_Logic_Vector) return Std_Logic;
    function HDLi_SLVtoI (X: std_logic_vector) return Natural;
    function HDLi_SLVtoI (X: std_logic) return Natural;

    function HDLi_ZeroExtend(X:Std_Logic_Vector; LENGTH : positive) return Std_Logic_Vector;
    function HDLi_ZeroExtend(X:Std_Logic; LENGTH : positive) return Std_Logic_Vector;

    function HDLi_OneExtend(X:Std_Logic_Vector; LENGTH : positive) return Std_Logic_Vector;
    function HDLi_OneExtend(X:Std_Logic; LENGTH : positive) return Std_Logic_Vector;

    function HDLi_SignExtend (X: Std_Logic_Vector; LENGTH : positive) return Std_Logic_Vector;
    function HDLi_SignExtend (X: Std_Logic; LENGTH : positive) return Std_Logic_Vector;
    function HDLi_2sComp_Extend (X: Std_Logic_vector; LENGTH : positive) return Std_Logic_Vector;
    function HDLi_2sComp_Extend (X: Std_Logic; LENGTH : positive) return Std_Logic_Vector;


    function "+"(A, B:Std_Logic_Vector) return Std_Logic_Vector;
    function "+"(A:std_Logic_Vector; B:Std_Logic) return Std_Logic_Vector;
    function "+"(A:std_logic; B:Std_Logic_Vector) return Std_Logic_Vector;

    function "-"(A, B:Std_Logic_Vector) return Std_Logic_Vector;
    function "-"(A:std_Logic_Vector; B:Std_Logic) return Std_Logic_Vector;
    function "-"(A:std_logic; B:Std_Logic_Vector) return Std_Logic_Vector;
    function "-"(A:std_logic_Vector) return Std_Logic_Vector;

    function HDLi_SUmult(A, B: Std_Logic_Vector) return Std_Logic_Vector;
    function HDLi_Smult(A, B: Std_Logic_Vector) return Std_Logic_Vector;
    function HDLi_Umult(A, B: Std_Logic_Vector) return Std_Logic_Vector;

    function HDLi_GreyIncr(A: Std_Logic_Vector) return Std_Logic_Vector;

    function HDLi_AltB_Signed(A, B: Std_Logic_Vector) return Std_Logic;
    function HDLi_AleB_Signed(A, B: Std_Logic_Vector) return Std_Logic;
    function HDLi_AgtB_Signed(A, B: Std_Logic_Vector) return Std_Logic;
    function HDLi_AgeB_Signed(A, B: Std_Logic_Vector) return Std_Logic;

    function HDLi_AltB_UnSigned(A, B: Std_Logic_Vector) return Std_Logic;
    function HDLi_AleB_UnSigned(A, B: Std_Logic_Vector) return Std_Logic;
    function HDLi_AgtB_UnSigned(A, B: Std_Logic_Vector) return Std_Logic;
    function HDLi_AgeB_UnSigned(A, B: Std_Logic_Vector) return Std_Logic;

    function HDLi_AeqB(A, B: Std_Logic_Vector) return Std_Logic;

end HDLI;

-----------------------------------------------------------------------
-- HDLI package body --
------------------------------

package body HDLI is


    function HDLi_Reduce_Xor (INPUT: Std_Logic_Vector) return Std_Logic is
        variable RESULT : Std_Logic;
    begin
      RESULT := '0';
      for j in INPUT'range loop
        RESULT := INPUT(j) xor RESULT;
        exit when RESULT = 'X';
      end loop;
      return RESULT;
    end;

    function HDLi_Reduce_And (INPUT: Std_Logic_Vector) return Std_Logic is
        variable RESULT : Std_Logic;
    begin
      RESULT := '1';
      for j in INPUT'range loop
        RESULT := INPUT(j) and RESULT;
        exit when RESULT = 'X';
      end loop;
      return RESULT;
    end;
  
    function HDLi_SLVtoI (X: std_logic_vector) return Natural is
          variable RESULT: integer;
    begin
      RESULT := 0;
      for I in X'range loop
        if X(I) = '1' then
          RESULT := 2*RESULT+1;
        else
          RESULT := 2*RESULT;
        end if;
      end loop;
      return RESULT;
    end;

    function HDLi_SLVtoI (X: std_logic) return Natural is
          variable RESULT: integer;
    begin
        if X = '1' then
          RESULT := 1;
        else
          RESULT := 0;
        end if;
      return RESULT;
    end;
    
    function Max(LEFT, RIGHT : integer) return integer is
    begin
        if left > right then
            return left;
        else
            return right;
        end if;
    end;



    function HDLi_OneExtend (X: Std_Logic_Vector; LENGTH : positive) return Std_Logic_Vector is
        variable result : Std_Logic_Vector (LENGTH-1 downto 0);
	constant XLEN : integer := X'length;
	alias X1: Std_Logic_Vector(XLEN-1 downto 0) is x;
    begin

        for I in result'range loop
            if (I < XLEN) then
              result(I) := X1(I);
            else
              result(I) := '1';
            end if;
        end loop;

        return (result);

    end;


    function HDLi_OneExtend (X: Std_Logic; LENGTH : positive) return Std_Logic_Vector is
        variable result : Std_Logic_Vector (LENGTH-1 downto 0);
    begin

        for I in result'range loop
            if (I < 1) then
              result(I) := x;
            else
              result(I) := '1';
            end if;
        end loop;

        return (result);

    end;


    function HDLi_ZeroExtend (X: Std_Logic_Vector; LENGTH : positive) return Std_Logic_Vector is
        variable result : Std_Logic_Vector (LENGTH-1 downto 0);
	constant XLEN : integer := X'length;
	alias X1: Std_Logic_Vector(XLEN-1 downto 0) is x;
    begin

        for I in result'range loop
            if (I < XLEN) then
              result(I) := X1(I);
            else
              result(I) := '0';
            end if;
        end loop;

        return (result);

    end;

    function HDLi_ZeroExtend (X: Std_Logic; LENGTH : positive) return Std_Logic_Vector is
        variable result : Std_Logic_Vector (LENGTH-1 downto 0);
    begin

        for I in result'range loop
            if (I < 1) then
              result(I) := x;
            else
              result(I) := '0';
            end if;
        end loop;

        return (result);

    end;

    function HDLi_SignExtend (X: Std_Logic_Vector; LENGTH : positive) return Std_Logic_Vector is
        variable result : Std_Logic_Vector (LENGTH-1 downto 0);
	constant XLEN : integer := X'length;
	alias X1: Std_Logic_Vector(XLEN-1 downto 0) is x;
    begin

        for I in result'range loop
            if (I < XLEN) then
              result(I) := X1(I);
            else
              result(I) := X1(X'length-1);
            end if;
        end loop;

        return (result);

    end;

    function HDLi_SignExtend (X: Std_Logic; LENGTH : positive) return Std_Logic_Vector is
        variable result : Std_Logic_Vector (LENGTH-1 downto 0);
    begin

        for I in result'range loop
            if (I < 1) then
              result(I) := x;
            else
              result(I) := x;
            end if;
        end loop;

        return (result);

    end;

    function HDLi_2sComp_Extend (X: Std_Logic_Vector; LENGTH : positive) return Std_Logic_Vector is
        variable result : Std_Logic_Vector (LENGTH-1 downto 0);
        variable temp : Std_Logic_Vector (LENGTH-1 downto 0);
	constant XLEN : integer := X'length;
	alias X1: Std_Logic_Vector(XLEN-1 downto 0) is X;
    begin

        for I in temp'range loop
            if (I < XLEN) then
              temp(I) := not(X1(I));
            else
              temp(I) := '0';
            end if;
        end loop;

        result := temp + '1';

        return (result);

    end;

    function HDLi_2sComp_Extend (X: Std_Logic; LENGTH : positive) return Std_Logic_Vector is
        variable result : Std_Logic_Vector (LENGTH-1 downto 0);
        variable temp : Std_Logic_Vector (LENGTH-1 downto 0);
    begin

        for I in temp'range loop
            if (I < 1) then
              temp(I) := not(x);
            else
              temp(I) := '0';
            end if;
        end loop;

        result := temp + '1';

        return (result);

    end;


 
------------------------------------------------------------------------
    function "+" (A, B: Std_Logic_Vector) return Std_Logic_Vector is
        constant LEN : integer := max(A'length,B'length);
        variable RESULT,left,right : Std_Logic_Vector( LEN-1 downto 0);
        variable carry: std_logic;
        variable lt, rt: std_logic;

    begin
        left := HDLi_ZeroExtend(A,result'length);
        right := HDLi_ZeroExtend(B,result'length);
        carry := '0';

        for I in RESULT'reverse_range loop
            lt := left(I);
            rt := right(I);
            RESULT(I) := lt xor rt xor carry;
            carry := (lt and rt) or (lt and carry) or (rt and carry);
        end loop;
        return RESULT;
    end;


    function "+" (A: std_logic_Vector; B: std_logic)
    return std_logic_Vector is
        variable RESULT: std_logic_Vector(A'length-1 downto 0);
    begin
        result := A;
        if not (B='1' or B='H') then return result; end if;
        for I in RESULT'reverse_range loop
            result(i) := not A(i);
            exit when result(i)='1';
        end loop;