usb_new_vsc9_ram_pkg.vhd

实现USB接口功能的VHDL和verilog完整源代码

-- HDLi Version 5.0 IP Bundle 2000.12.15
-- Top HDL file name is usb_new.vhd
-- -----------------------------------------------------------------------------
--                          Royal Philips Electronics
-- -----------------------------------------------------------------------------
-- Copyright 2001 by Royal Philips Electronics All rights reserved.
-- 
-- This module is property of Royal Philips Electronics (Philips) and its use
-- is granted to the customer for the sole purpose of implementing in silicon
-- provided by Philips.   This module may only be used in accordance with the
-- provisions of the HDLi License Agreement.
-- 
-- -----------------------------------------------------------------------------
--                           USBFS22 Device Version 1.0
-- -----------------------------------------------------------------------------
-- usb_new/data/USBFS22/RTL/usb_new_vsc9_ram_pkg.vhd : RTL VHDL
--
-- Compiled by arkrish on Tue Apr  3 17:23:42 2001
-- -----------------------------------------------------------------------------
-- HDLi Version 5.0 IP Bundle 2000.12.15
-- Top HDL file name is vsc9_ram.vhd
-- -----------------------------------------------------------------------------
--                          Royal Philips Electronics
-- -----------------------------------------------------------------------------
-- Copyright 2001 by Royal Philips Electronics All rights reserved.
-- 
-- This module is property of Royal Philips Electronics (Philips) and its use
-- is granted to the customer for the sole purpose of implementing in silicon
-- provided by Philips.   This module may only be used in accordance with the
-- provisions of the HDLi License Agreement.
-- 
-- -----------------------------------------------------------------------------
--                         BIST SRAM Template Version 2.4
-- -----------------------------------------------------------------------------
-- vsc9_ram_pkg.vhd : RTL VHDL
--
-- Compiled by arkrish on Tue Apr  3 11:53:35 2001
-- -----------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

package vsc9_ram_pkg is

   component vsc9_ram
      port ( tck : in  STD_LOGIC;
             ntrst : in  STD_LOGIC;
             tbe : in  STD_LOGIC;
             trunbist : in  STD_LOGIC;
             tseir : in  STD_LOGIC;
             tsedr : in  STD_LOGIC;
             tdi : in  STD_LOGIC;
             tdo : out STD_LOGIC;
             tend : out STD_LOGIC;
             chb : out STD_LOGIC_VECTOR(15 downto 0);
             dri : in  STD_LOGIC;
             dro : out STD_LOGIC);

   end component;

  -- DEFINE THE STATE OF THE TEST SEQUENCE
  type state_type is
         (
          st_init,     -- init state
          d1_w0,       -- +(w0)         pattern 55/aa
          d1_r0u,      -- +(r0, w1, r1) pattern 55/aa
          d1_r1u,      -- +(r1, w0, r0) pattern 55/aa
          d1_r0d,      -- -(r0, w1, r1) pattern 55/aa
          d1_r1d,      -- -(r1, w0, r0) pattern 55/aa
          d2_w0,       -- +(w0)         pattern 00/ff
          d2_r0u,      -- +(r0, w1, r1) pattern 00/ff
          d2_r1u,      -- +(r1, w0, r0) pattern 00/ff
          d2_r0d,      -- -(r0, w1, r1) pattern 00/ff
          d2_r1d,      -- -(r1, w0, r0) pattern 00/ff
          st_end,      -- end state
	  st_done,     -- done state
          st_idle);    -- idle state

  -- DEFINE THE STATE OF THE MARCH
  CONSTANT IDLESTATE:      STD_LOGIC_VECTOR(2 downto 0) := "000"; -- idle and init state
  CONSTANT WRITESTATE0:    STD_LOGIC_VECTOR(2 downto 0) := "101"; -- write state in (W) or (r,W) or (r,W,r)
  CONSTANT WRITESTATE:     STD_LOGIC_VECTOR(2 downto 0) := "001"; -- write state in (W) or (r,W) or (r,W,r)
  CONSTANT LASTREADSTATE:  STD_LOGIC_VECTOR(2 downto 0) := "010"; -- last read state in (r,w,R)
  CONSTANT FIRSTREADSTATE: STD_LOGIC_VECTOR(2 downto 0) := "011"; -- first read state in (R,w) or (R,w,r)
  CONSTANT FIRSTREADSTATE0:STD_LOGIC_VECTOR(2 downto 0) := "111"; -- first read state in (R,w) or (R,w,r)

  -- DEFINE THE TYPE OF THE MARCH
  CONSTANT W_CYCLE: STD_LOGIC_VECTOR(1 downto 0) := "00";
  CONSTANT RW_CYCLE: STD_LOGIC_VECTOR(1 downto 0) := "01";
  CONSTANT RWR_CYCLE: STD_LOGIC_VECTOR(1 downto 0) := "10";

  -- DEFINE THE PATTERN TYPES
  CONSTANT PAT_TYPE_00: STD_LOGIC_VECTOR(1 downto 0) := "00";
  CONSTANT PAT_TYPE_FF: STD_LOGIC_VECTOR(1 downto 0) := "01";
  CONSTANT PAT_TYPE_55: STD_LOGIC_VECTOR(1 downto 0) := "10";
  CONSTANT PAT_TYPE_AA: STD_LOGIC_VECTOR(1 downto 0) := "11";

  CONSTANT MAXADDRBITS: integer := 7;

end vsc9_ram_pkg;


package body vsc9_ram_pkg is

end vsc9_ram_pkg;