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📄 usb_new_usbpvci_str.vhdl

📁 实现USB接口功能的VHDL和verilog完整源代码
💻 VHDL
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signal  Configured_LED:          one_bit;
signal  DH_Connect:              boolean;

signal  EX_NeedClock:            boolean;
signal  FsClk:                   one_bit;
signal  HB_UsbDifBit:            one_bit;
signal  HB_UsbLineBits:          two_bits;
signal  HC_ResetDevice:          booleans(N_EMBEDDED_PORTS -1 downto 0);

signal  PINConfigArray:          S_PINConfigArray;
signal  PU_Reset_N:              one_bit;

signal  RxRAM_A:                 RxRAMAddr_bits;
signal  RxRAM_DQ_In:             four_bytes;
signal  RxRAM_DQ_Out:            four_bytes;
signal  RxRAM_E_N:               one_bit;
signal  RxRAM_G_N:               one_bit;
signal  RxRAM_W_N:               one_bit;
signal  TxRAM_A:                 TxRAMAddr_bits;
signal  TxRAM_DQ_In:             four_bytes;
signal  TxRAM_DQ_Out:            four_bytes;
signal  TxRAM_E_N:               one_bit;
signal  TxRAM_G_N:               one_bit;
signal  TxRAM_W_N:               one_bit;

signal  RG_BUSReset:             boolean;
signal  RemoteWakeup:            boolean;
signal  Reset12MHzRef_N:         one_bit;
signal  SIE_LowSpeedTransaction: boolean;
signal  SIE_RxUsbLogValue:       T_UsbLog_enum;
signal  SIE_TxLogValue:          T_UsbLog_enum;
signal  SIE_UsbEnable_N:         one_bit;
signal  Suspend_In:              boolean;
signal  TM_ClockOn:              one_bit;
signal  TM_ClockRestarted:       boolean;
signal  TM_EOF2:                 boolean;
signal  TM_Idle5ms:              boolean;
signal  TM_IsoToggle:            integer range 0 to 1;
signal  TestMode:                one_bit;
signal  UP_DM:                   one_bit;
signal  UP_DP:                   one_bit;
signal  UP_DsLineBits:           two_bits;

signal  USB_FrameClock:          one_bit;
signal  USB_Reset_O_N:           one_bit;
signal  USB_Suspended:           one_bit;
signal  VBusAvailable:           boolean;
signal  USB_clk:                 one_bit;
signal  USB_reset_n:             one_bit;
signal  USB_req:                 one_bit;
signal  USB_rnw:                 one_bit;
signal  USB_gnt:                 one_bit;
signal  USB_address:             byte;
signal  USB_w_data:              four_bytes;
signal  USB_r_data:              four_bytes;
signal  Int_Req_Gen:             one_bit;
signal  Int_Req_Iso:             one_bit;
signal  pvci_reset_n_out:        std_logic;

BEGIN

  GLUE_1: GLUE
     port map(
              -- APB interface
              clk                      =>  clk,  
              USB_clk                  =>  USB_clk,   
              pvci_reset_n             =>  pvci_reset_n,
              USB_reset_n              =>  USB_reset_n,		  
              req                      =>  req,
              USB_req                  =>  USB_req,
              address                  =>  address,
              USB_address              =>  USB_address,
              rnw                      =>  rnw, 
              USB_rnw                  =>  USB_rnw,  
              w_data                   =>  w_data,
              USB_w_data               =>  USB_w_data,
              gnt                      =>  gnt,
              USB_gnt                  =>  USB_gnt,
              r_data                   =>  r_data,
              USB_r_data               =>  USB_r_data,
	      pvci_reset_n_out         =>  pvci_reset_n_out,
	      USB_AsynReset_N          =>  USB_AsynReset_N,
              
	      -- Interrupt signals
              Intr_Request_Irq         => Int_Req_Gen, 
              USB_Int_Req_Irq          => USB_Int_Req_Irq,
              Intr_Request_Fiq         => Int_Req_Iso,
              USB_Int_Req_Fiq          => USB_Int_Req_Fiq,    
              
	      ---------- Clocks ---------
              Clk12MHzRef              =>    Clk12MHzRef,
              Clk12MHzRef_O            =>    Clk12MHzRef_O,
              Clk12MHz_O               =>    Clk12MHz_O,
              Clk48MHz                 =>    Clk48MHz,
              USB_NeedClk              =>    USB_NeedClk,
          
              DH_Connect               =>    DH_Connect,
              FsClk                    =>    FsClk,
              HB_UsbLineBits           =>    HB_UsbLineBits,  
              HB_UsbDifBit             =>    HB_UsbDifBit,  
              HC_ResetDevice           =>    HC_ResetDevice,
              USB_BitClk               =>    USB_BitClk,
              USB_BitClk_Out           =>    USB_BitClk_Out,
              USB_MainClk              =>    USB_MainClk,
          
              ---------- Connect ---------
              USB_Connect_N            =>    USB_Connect_N,
              USB_VBus                 =>    USB_VBus,
          
              ---------- Misc ---------
              ChipID                   =>    ChipID,
              PINConfigArray           =>    PINConfigArray,
      
              Suspend_In               =>    Suspend_In,
              TestMode                 =>    TestMode,
              USB_Reset_O_N            =>    USB_Reset_O_N,
              USB_Suspended            =>    USB_Suspended,
              USB_TestMode             =>    USB_TestMode,
              VBusAvailable            =>    VBusAvailable,
          
              ---------- Open ---------
              CR_DebugRecDataN         =>    CR_DebugRecDataN,
              CR_DebugRecDataP         =>    CR_DebugRecDataP,
              Reset12MHzRef_N          =>    Reset12MHzRef_N,
              SIE_RxUsbLogValue        =>    SIE_RxUsbLogValue,
              TM_ClockOn               =>    TM_ClockOn,
              TM_ClockRestarted        =>    TM_ClockRestarted,
              TM_Idle5ms               =>    TM_Idle5ms,
           
              ---------- Raminterface ---------
              RxRAM_E_N                =>    RxRAM_E_N,
              RxRAM_W_N                =>    RxRAM_W_N,
              RxRAM_G_N                =>    RxRAM_G_N,
              RxRAM_A                  =>    RxRAM_A,
              RxRAM_DQ_In              =>    RxRAM_DQ_In,
              RxRAM_DQ_Out             =>    RxRAM_DQ_Out,
            
              TxRAM_E_N                =>    TxRAM_E_N,
              TxRAM_W_N                =>    TxRAM_W_N,
              TxRAM_G_N                =>    TxRAM_G_N,
              TxRAM_A                  =>    TxRAM_A,
              TxRAM_DQ_In              =>    TxRAM_DQ_In,
              TxRAM_DQ_Out             =>    TxRAM_DQ_Out,
             
              USB_RxRAM_E_N            =>    USB_RxRAM_E_N,
              USB_RxRAM_W_N            =>    USB_RxRAM_W_N,
              USB_RxRAM_G_N            =>    USB_RxRAM_G_N,
              USB_RxRAM_A              =>    USB_RxRAM_A,
              USB_RxRAM_DQ_In          =>    USB_RxRAM_DQ_In,
              USB_RxRAM_DQ_Out         =>    USB_RxRAM_DQ_Out,
           
              USB_TxRAM_E_N            =>    USB_TxRAM_E_N,
              USB_TxRAM_W_N            =>    USB_TxRAM_W_N,
              USB_TxRAM_G_N            =>    USB_TxRAM_G_N,
              USB_TxRAM_A              =>    USB_TxRAM_A,
              USB_TxRAM_DQ_In          =>    USB_TxRAM_DQ_In,
              USB_TxRAM_DQ_Out         =>    USB_TxRAM_DQ_Out,
          
              ---------- Suspend ---------
              USB_Suspend              =>    USB_Suspend,
           
              SIE_UsbEnable_N          => SIE_UsbEnable_N,  
              TM_EOF2                  => TM_EOF2,  
              RemoteWakeup             => RemoteWakeup,  
              SIE_LowSpeedTransaction  => SIE_LowSpeedTransaction,  
              RG_BUSReset              => RG_BUSReset,  
              TM_IsoToggle             => TM_IsoToggle,
           
              ---------- Upstream port ---------
              Configured_LED           => Configured_LED,
              UP_DM                    => UP_DM,
              UP_DP                    => UP_DP,
              UP_DsLineBits            => UP_DsLineBits,
              USB_FrameClock           => USB_FrameClock,  
              USB_UP_LED_N             => USB_UP_LED_N,
              USB_UP_RxDM              => USB_UP_RxDM,
              USB_UP_RxDP              => USB_UP_RxDP,
              USB_UP_RxRCV             => USB_UP_RxRCV,
              USB_UP_TxDM              => USB_UP_TxDM,
              USB_UP_TxDP              => USB_UP_TxDP,
              USB_UP_TxEnable_N        => USB_UP_TxEnable_N
              
             );

   TX_SF_DPDM_1: TX_SF_DPDM
     port map(
              SIE_TxLogValue           => SIE_TxLogValue,
              UP_DP                    => UP_DP,	      -- Glue
              UP_DM                    => UP_DM,	      -- Glue
              ConfigArray              => ConfigArray
             );

   USB_INT_1: USB_INT
     port map(
              -- APB interface
              clk                      =>  USB_clk, 
              pvci_reset_n             =>  pvci_reset_n_out,        
              req                      =>  USB_req,
              address                  =>  USB_address,
              rnw                      =>  USB_rnw,  
              w_data                   =>  USB_w_data,
              gnt                      =>  USB_gnt,
              r_data                   =>  USB_r_data,
              error                    =>  error,
       
	      -- Interrupt signals
              Intr_Request_Irq         => Int_Req_Gen, 
              Intr_Request_Fiq         => Int_Req_Iso, 
         
              -- Clock Outputs
              Clk12MHzRef_O            => Clk12MHzRef_O,
              Clk12MHz_O               => Clk12MHz_O,
    
              -- Configuration Info 
              ChipID                   => ChipID,
              ConfigArray              => ConfigArray,
              PINConfigArray           => PINConfigArray,
    
              -- Connection to RAM
              RxRAM_E_N                => RxRAM_E_N,
              RxRAM_W_N                => RxRAM_W_N,
              RxRAM_G_N                => RxRAM_G_N,
              RxRAM_A                  => RxRAM_A,
              RxRAM_DQ_In              => RxRAM_DQ_In,
              RxRAM_DQ_Out             => RxRAM_DQ_Out,
    
              TxRAM_E_N                => TxRAM_E_N,
              TxRAM_W_N                => TxRAM_W_N,
              TxRAM_G_N                => TxRAM_G_N,
              TxRAM_A                  => TxRAM_A,
              TxRAM_DQ_In              => TxRAM_DQ_In,
              TxRAM_DQ_Out             => TxRAM_DQ_Out,
    
              -- Control Signals
              SIE_LowSpeedTransaction  => SIE_LowSpeedTransaction,
              SIE_RxUsbLogValue        => SIE_RxUsbLogValue,
    
              -- Device State
              -- DH_Interrupt          => boolean,
    
              -- For Debugger
              CR_DebugRecDataN         => CR_DebugRecDataN,
              CR_DebugRecDataP         => CR_DebugRecDataP,
    
              -- Frame Timer
              TM_EOF2                  => TM_EOF2,
    
              -- generated reset signals
              RG_BUSReset              => RG_BUSReset,
              Reset12MHzRef_N          => Reset12MHzRef_N,
              USB_Reset_O_N            => USB_Reset_O_N,
    
              -- Input from Hub or Upstream Port
              HB_UsbDifBit             => HB_UsbDifBit,
              HB_UsbLineBits           => HB_UsbLineBits,
    
              -- reset
              PU_Reset_N               => USB_reset_n,
              UP_DsLineBits            => UP_DsLineBits,

              -- LED control
              Configured_LED           => Configured_LED,
    
              -- Signals to other USBINT blocks
              HC_ResetDevice           => HC_ResetDevice,
    
              -- Soft Connect
              DH_Connect               => DH_Connect,
              VBusAvailable            => VBusAvailable,
    
              -- Suspend/Wake up
              EX_NeedClock             => EX_NeedClock,
              RemoteWakeup             => RemoteWakeup,
              Suspend_In               => Suspend_In,
              TM_ClockOn               => TM_ClockOn,
              TM_ClockRestarted        => TM_ClockRestarted,
              TM_Idle5ms               => TM_Idle5ms,

              USB_Suspended            => USB_Suspended,
    
              -- system
              Clk12MHzRef              => Clk12MHzRef,
              Clk48MHz                 => Clk48MHz,
    
              -- System
              FsClk                    => FsClk,
              TM_IsoToggle             => TM_IsoToggle,

              TestMode                 => TestMode,
              USB_FrameClock           => USB_FrameClock,
    
              -- To USB bus
              SIE_TxLogValue           => SIE_TxLogValue,
              SIE_UsbEnable_N          => SIE_UsbEnable_N
    
             );

EX_NeedClock <= FALSE;

end STR;

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