smarti_box.v

实现USB接口功能的VHDL和verilog完整源代码

`include "smarti_params.v"
/********************************************************
 *       1. Filename : smarti.v
 *       2. Author   : Rha, haeyoung
 *       3. Key Feature : interface between USB and smart card.
 *       4. created date : 99/7/27
 *       5. modification history
 *            -1. remove reset condition
 *            -2. multipage write/read
 *            -3. data in & write command('h10) in one control tr
 *            -4. read/write unit : page  => dummy read/dummy wr 
 ********************************************************/

module smarti_box (
                mcclock, 
	        // from usb
                mcreset, 
                sm_enable, 
                disablebus, 
                sm64_enable, 
                cmdrdready, 
                statuswrready, 
                getdata, 
                getstatus, 
                getbusy, 
                datardready, 
                datawrready, 
                cmddata,
                datarddata,
                
	        // from smart card
                card_ready,
                smart_rd_data,

	        // to usb
                cmdrd, 
                statuswr, 
                statusdata, 
                datard, 
                datawr, 
                datawrdata, 

	        // to smart_card
                ale,
                cle,
                reb,
                web,
                out_enable,
                smart_wr_data
              );


  input              mcclock;
  input              mcreset; 
  input              disablebus; 
  input              cmdrdready; 
  input              statuswrready; 
  input              getdata; 
  input              getstatus; 
  input              getbusy; 
  input              datardready; 
  input              datawrready; 
  input        [7:0] cmddata;
  input        [7:0] datarddata;
  input              card_ready;
  input              sm_enable;
  input              sm64_enable;
  input        [7:0] smart_rd_data;


  output             cmdrd;
  output             statuswr; 
  output       [7:0] statusdata; 
  output             datard; 
  output             datawr;
  output       [7:0] datawrdata; 
  output             ale;
  output             cle;
  output             reb;
  output             web;
  output             out_enable;
  output       [7:0] smart_wr_data; 

  wire               cmdrd = ~sm_enable;
  wire               statuswr = ~cmdrdready && disablebus; 
  wire         [7:0] statusdata = ~cmddata; 
  wire               datard = ~getdata ; 
  wire               datawr = ~getstatus;
  wire         [7:0] datawrdata = ~datarddata ;
  wire               ale = ~getbusy;
  //wire               ceb = ~datardready;
  wire               cle = ~datawrready || ~datardready;
  wire               reb = ~card_ready || sm_enable || sm64_enable ;
  wire               web = ~statuswrready;
  //wire               wpb = ~statuswrready;
  wire               out_enable = ~card_ready;
  wire         [7:0] smart_wr_data = 8'b0 ;

 endmodule