smarti.v

实现USB接口功能的VHDL和verilog完整源代码

`include "smarti_params.v"
/********************************************************
 *       1. Filename : smarti.v
 *       2. Author   : Rha, haeyoung
 *       3. Key Feature : interface between USB and smart card.
 *       4. created date : 99/7/27
 *       5. modification history
 *            -1. remove reset condition
 *            -2. multipage write/read
 *            -3. data in & write command('h10) in one control tr
 *            -4. read/write unit : page  => dummy read/dummy wr 
 *            -5. remove wpb, ceb ==> gpio signal 99.12.8
 ********************************************************/

module smarti (
                mcclock, 
	        // from usb
                mcreset, 
                //mcreset_usb, 
                sm_enable, 
                sof, 
                sm64_enable, 
                disablebus, 
                cmdrdready, 
                statuswrready, 
                getdata, 
                getstatus, 
                getbusy, 
                datardready, 
                datawrready, 
                cmddata,
                datarddata,
                
	        // from smart card
                card_ready,
                smart_rd_data,

	        // to usb
                cmdrd, 
                statuswr, 
                statusdata, 
                datard, 
                datawr, 
                datawrdata, 

	        // to smart_card
                ale,
                //ceb,
                cle,
                reb,
                web,
                //wpb,
                out_enable,
                smart_wr_data
              );


  input              mcclock;
  input              mcreset; 
  input              sm_enable; 
  input              sm64_enable; 
  input              sof; 
  input              disablebus; 
  input              cmdrdready; 
  input              statuswrready; 
  input              getdata; 
  input              getstatus; 
  input              getbusy; 
  input              datardready; 
  input              datawrready; 
  input        [7:0] cmddata;
  input        [7:0] datarddata;
  input              card_ready;
  input        [7:0] smart_rd_data;

  output             cmdrd;
  output             statuswr; 
  output       [7:0] statusdata; 
  output             datard; 
  output             datawr;
  output       [7:0] datawrdata; 
  output             ale;
  //output             ceb;
  output             cle;
  output             reb;
  output             web;
  //output             wpb;
  output             out_enable;
  output       [7:0] smart_wr_data; 
  
  reg                getdata_d;
  reg                card_ready_d;
  reg                card_ok;
  reg                statusrd_done;
  reg                statusrd_d;
  reg                cmdrd;
  reg                statuswr;
  reg          [7:0] statusdata;
  reg          [6:0] sm_status;
  //reg          [7:0] sm_status;
  //reg          [7:0] busy_status;
  reg          [4:0] num_sof;
  reg                busy_timeout ;
  reg                datard;
  reg                datawr;
  reg          [7:0] datawrdata; 
  reg          [7:0] smart_wr_data; 
  reg                ale,cle,reb,web;
  //reg                ale,ceb,cle,reb,web;
  reg                new_page ;
  reg          [3:0] sm_state;
  reg          [3:0] nxt_sm_state;
  reg          [1:0] clk_cnt;
  reg          [1:0] st_cnt;
  reg          [4:0] err_cnt;
  reg                cmdrd_c;
  wire               datard_c;
  reg 		     reset_cnt;
  wire	             reset_cmd_num;
  reg 		     out_enable;
  reg          [9:0] num_sent;
  reg         [31:0] addr ;
  reg          [7:0] command;
  reg          [7:0] hidden_cmd0 ;
  reg          [7:0] hidden_cmd1 ;
  reg          [2:0] cmd_num;
  reg         [7:0] command_c;
  //wire         [7:0] command_c;
  wire               out_enable_c;
  wire               read_cmd;
  wire         [1:0] num_addr;
  wire               ale_c, cle_c,reb_c, web_c ;
  wire               statuswr_c ;
  //reg                interface_reset ;
  reg                sm64_en_d ;
  reg                escape_busy ;

  parameter [3:0] //synopsys enum state_info
    IDLE = 4'b0000,
    CMD  = 4'b0001,
    ADDR  = 4'b0010,
    RD_CMD  = 4'b0011,
    GET_STATUS  = 4'b0100,
    WR_STATUS  = 4'b0101,
    READ  = 4'b0110,
    WRITE  = 4'b0111,
    DUMMY_WR  = 4'b1001,
    WAIT_SM  = 4'b1011,
    DUMMY_RD  = 4'b1010,
    HIDDEN_CMD  = 4'b1000;

  parameter [7:0]
    DATA_IN = 8'h80,
    READ11 = 8'h00,
    READ12 = 8'h01,
    READ2  = 8'h50,
    READ_ID = 8'h90,
    RESET = 8'hff,
    PROGRAM  = 8'h10,
    ERASE_SETUP = 8'h60,
    ERASE = 8'hd0,
    READ_STATUS = 8'h70;

  parameter  num_send = 528; 

   /* // synopsys sync_set_reset "mcreset" */
  always @( posedge mcclock ) begin
    if ( mcreset ) begin
      cmdrd <= 0;
      statuswr <= 0;
      datard <=  0;
      datawr <=  0;
      reb <=  1;
      web <=  1;
      ale <=  0;
      cle <=  0;
      out_enable <= 0;
      escape_busy <= 0;
    end
    else if ( sm_enable )begin
      cmdrd <= cmdrd_c ;
      statuswr <= ( sm_state == WR_STATUS && clk_cnt == 1 ) ? 1:0;
      datard <=   ( ( sm_state == DUMMY_WR || sm_state == WRITE ) && 
                      clk_cnt == 'b0 && datardready ) ? 1 : 0 ;
      datawr <=  (( sm_state == READ || sm_state == DUMMY_RD ) && 
                    datawrready && clk_cnt =='b1) ? 1 : 0 ;
      escape_busy <= ( sm_state == RD_CMD ) ? 0 : 
                 (( !card_ready_d && num_sof[4:1] == 4'b1111 ) ? 1: escape_busy);
                 //(( sm_state == WAIT_SM && num_sof[4:1] == 4'b1111 ) ? 1: escape_busy);
      //reb <=  ( (sm_state == READ &&  clk_cnt =='b0 && datawrready && card_ready_d )||  12.28
      reb <=  ( (sm_state == READ &&  clk_cnt =='b0 && datawrready && card_ok )|| 
                (sm_state == GET_STATUS && clk_cnt =='b0 ) ||
                (sm_state == WR_STATUS && clk_cnt =='b0 && command == READ_ID ) ) ? 0 : 1; 
      web <= ((sm_state == CMD || sm_state == ADDR || sm_state == HIDDEN_CMD ||
                  sm_state == WRITE ) && clk_cnt ==1 )? 0 : 1 ;
      ale <=  ( sm_state == ADDR) ? 1 : 0 ;
      cle <=  ( (sm_state == CMD || sm_state == HIDDEN_CMD) && clk_cnt != 'b11 ) ? 1 : 0 ;
      //wpb <=  1;
      out_enable <=(( sm_state == CMD ||sm_state == ADDR||sm_state == WRITE || sm_state == HIDDEN_CMD )&&
                         ( clk_cnt == 'b10 || clk_cnt == 'b1 ) && !disablebus ) ? 1: 0;
    end
  end

  always @( posedge mcclock ) begin
    statusrd_d <= ( getbusy || getstatus ) && sm_enable;
    getdata_d <= getdata && sm_enable;
    card_ok <= card_ready || escape_busy ;
    card_ready_d <= card_ready ;
    sm64_en_d <= ( sm_enable  &&  sm64_enable ) ;
  end 

  always @( posedge mcclock ) begin
    if ( mcreset ) begin
      statusrd_done <= 1;
    end
    else begin
      statusrd_done <= ( (getbusy || getstatus)  && !statusrd_d ) ? 0 : 
                    (( sm_state == WR_STATUS && nxt_sm_state == IDLE && !statusrd_done ) ?
                     1:statusrd_done);
    end 
  end 
      
  always @( posedge mcclock ) begin
    if ( sm_state == WR_STATUS && clk_cnt == 'b01 && getstatus && command != READ_ID) begin
      statusdata <=  {escape_busy,sm_status} ;
    end 
    else if ( sm_state == WR_STATUS && clk_cnt == 'b01 && getstatus )
      statusdata <= smart_rd_data;
    else if ( sm_state == WR_STATUS && clk_cnt == 'b01 && getbusy)
      statusdata <= {7'h0,card_ready_d};
    else 
      statusdata <= statusdata;
    if ( sm_state == READ && clk_cnt == 'b01)
      datawrdata <= smart_rd_data;
    else
      datawrdata <= datawrdata;

    if ( sm_state == CMD && clk_cnt == 'b0)
      smart_wr_data <= command ;
    else if ( sm_state == HIDDEN_CMD && clk_cnt == 'b0 && st_cnt == 0 )
      smart_wr_data <= hidden_cmd0 ;
    else if ( sm_state == HIDDEN_CMD && clk_cnt == 'b0 && st_cnt == 1 )
      smart_wr_data <= hidden_cmd1 ;
    else if ( sm_state == ADDR && clk_cnt == 'b0 && st_cnt == 'b0 )
      smart_wr_data <= addr[7:0] ;
    else if ( sm_state == ADDR && clk_cnt == 'b0 && st_cnt == 'b1 )
      smart_wr_data <= addr[15:8];
    else if ( sm_state == ADDR && clk_cnt == 'b0 && st_cnt == 'b10 )
      smart_wr_data <= addr[23:16];
    else if ( sm_state == ADDR && clk_cnt == 'b0 && st_cnt == 'b11 )
      smart_wr_data <= addr[31:24];
    else if ( sm_state == WRITE  && clk_cnt == 'b1)  
      smart_wr_data <= datarddata;
    else
      smart_wr_data <= smart_wr_data;
  end

  always @( posedge mcclock ) begin
    if ( mcreset ) 
      cmd_num  <= 'h0;
    else  if (  sm_state == RD_CMD  )
      cmd_num <=  cmd_num + 1;
    else  if ( reset_cmd_num)
      cmd_num <=  'h0;
    /*else
      cmd_num <=  cmd_num;*/
  end 

  always @( posedge mcclock ) begin
    if ( mcreset ) 
      sm_status <= 0; 
    else if ( sm_state == RD_CMD )
      sm_status <= 0; 
    else if (  sm_state == GET_STATUS && clk_cnt == 'b01 )
      sm_status <= sm_status + smart_rd_data[0]; 
  end 

  always @( posedge mcclock ) begin
    if ( mcreset )