tri_bus.v

来自「实现USB接口功能的VHDL和verilog完整源代码」· Verilog 代码 · 共 34 行

/********************************************************
 *    1. File name : tri_bus.v 
 *    2. Author    : Rha, haeyoung
 *    3. Key Feature & module : This module( tri_bus ) is
 *           for tri-state  bus between  usb and smart card.
 *
 *     4. created date : 99/7/29
 *     5. modification history
 ********************************************************/

module tri_bus (
                out_enableb, 
                // from smarti
                smart_wr_data,
                // from smart card
                io,
                // to smarti
                smart_rd_data
                // to smart card
              );

  input              out_enableb;
  input        [7:0] smart_wr_data;
  inout        [7:0] io;
  output       [7:0] smart_rd_data;
  //output       [7:0] wr_data;


  assign smart_rd_data = io ;
  //assign smart_rd_data = ( !out_enableb)? 'h0  :io;
  assign io   = ( !out_enableb)? smart_wr_data  : 'hz;

endmodule