data_transmit.v

实现USB接口功能的VHDL和verilog完整源代码

/*
# --------------------------------------------------------------------------
#    Module      : transmit.v 
#     
#    Revision     : $Revision: 1.17 $
#    
#---------------------------------------------------------------------------
#   Purpose : UNIT to transmit MMC command or data to card.
#-------------------------------------------------------------------------
*/

`include "usbmmc_variable.v"

module data_transmit	( 
                // input
                mask_transmit,
				setcmdwr,
				mmc_enable,
                clock_5m,
                sync_reset_uf_in,

                endp1rdready_uf_in,
                endp1rddata_uf_in,

                // output
                endp1rd_fu_out,
                endp1rddatadone_fu_out,
				multi_getdata,
                tmp_multi_getdata,
//                data_transmit_sync,
                data_transmit,
                dat_fc_out
                );
input                   mask_transmit;
input                   setcmdwr;	
input                   mmc_enable;
input                   clock_5m;
input                   sync_reset_uf_in;

input                   endp1rdready_uf_in;
input   [`BYTE:`LSB]    endp1rddata_uf_in;

output                  endp1rd_fu_out;
output                  endp1rddatadone_fu_out;
//output                  data_transmit_sync;
output                  data_transmit;
output                  dat_fc_out;
output                  multi_getdata;
output                  tmp_multi_getdata;
reg                     read_strobe;
reg     [`BYTE:`LSB]    transmit_byte;
reg     [`BYTE:`LSB]    temp_byte;
reg     [`BYTE:`LSB]    byte_counter;
reg     [`FOUR:`LSB]    bit_counter;
reg                     receive_temp;
reg                     saved;
reg                     data_transmit;
reg                     lock;
reg                     transmit_done;

reg                     endp1rddatadone_fu_out;
reg     [`TWO:`LSB]     dummy_count;
reg     [5:0]           block_count;
wire    [`BYTE:`LSB]    number_of_byte1;
wire                     dat_fc_out;
wire    [`BYTE:`LSB]    data_uf_in;
wire                    last_transaction;
wire                    dummy;
wire                    gen_rd_strobe;
wire                    lock_tem;
wire                    gen_temp;
wire                    ready_uf_in;
wire                    endp1rd_fu_out;

reg tmp_multi_getdata;
reg tmp_multi_getdata1;
reg tmp_multi_getdata2;
assign ready_uf_in = endp1rdready_uf_in && !tmp_multi_getdata;
assign data_uf_in = endp1rddata_uf_in;
assign number_of_byte1 = `THIRTY_TWO;
assign endp1rd_fu_out = read_strobe;

assign dummy = (endp1rdready_uf_in)? dummy_count[`TWO]: !dummy_count[`LSB];
assign gen_rd_strobe = ready_uf_in & lock & !transmit_done & dummy;

always @(negedge clock_5m)  // 16 bit dummy clock generation
  if(sync_reset_uf_in) dummy_count <= `DUMMY_COUNT_INITIAL;
    else if(!endp1rdready_uf_in) dummy_count <= `DUMMY_COUNT_INITIAL;
           else if(!dummy_count[`TWO]) dummy_count <= dummy_count + `HIGH;
                  else dummy_count <= dummy_count;

always @(posedge clock_5m)
  if(sync_reset_uf_in) read_strobe <= `LOW;
    else if(mmc_enable) read_strobe <= gen_rd_strobe;
           else read_strobe <= read_strobe;

always @(posedge clock_5m)
  if(sync_reset_uf_in) endp1rddatadone_fu_out <= `HIGH;
    else if(mmc_enable) 
           begin
           if(&byte_counter & lock_tem)
             endp1rddatadone_fu_out <= `HIGH;
             else 
               if(ready_uf_in) endp1rddatadone_fu_out <= `LOW;
                 else endp1rddatadone_fu_out <= endp1rddatadone_fu_out;
           end
           else endp1rddatadone_fu_out <= endp1rddatadone_fu_out;

assign lock_tem = (bit_counter == `GEN_LOCK) & !read_strobe;

always @(posedge clock_5m)
  if(sync_reset_uf_in) lock <= `HIGH;
    else if(mmc_enable) 
           begin
           if(gen_rd_strobe) lock <= ~gen_rd_strobe;
             else if(lock_tem) lock <= lock_tem;
                    else lock <= lock;
           end
           else lock <= lock;

assign	last_transaction = (byte_counter == number_of_byte1 );

// JAKE Counting Last_transition for detecting datard start points
reg tmpmask_transmit;

always@(posedge clock_5m)
  tmpmask_transmit <= !mask_transmit;

wire stop_receive = tmpmask_transmit && mask_transmit;

always @(posedge clock_5m)
if(sync_reset_uf_in|!setcmdwr)
   block_count <= 'h00;
else if(last_transaction) 
//else if(endp1rddatadone_fu_out && setcmdwr) 
//   block_count <= (block_count == 'd17) ? 'h00 : block_count + `HIGH; 
   block_count <=  block_count + `HIGH; 
else if(block_count == 'd17) block_count <= 'h00;
reg start_receive;

always@(posedge clock_5m)
   if(sync_reset_uf_in|!setcmdwr)
	   start_receive <=1'b0;
   else
	  start_receive <= (block_count == 'd17) ? 1'b1 : 1'b0;

always@(posedge clock_5m)
  if(sync_reset_uf_in)
     tmp_multi_getdata1 <='b0;
 else
	tmp_multi_getdata1 <= (start_receive) ? 1'b1 :(stop_receive) ? 1'b0:
					 tmp_multi_getdata1;
always @(posedge clock_5m)
  tmp_multi_getdata2 <= tmp_multi_getdata1;
always @(posedge clock_5m)
  tmp_multi_getdata <= tmp_multi_getdata2;

wire multi_getdata = (bit_counter =='h00) ? tmp_multi_getdata1 : 1'b0;
always @(posedge clock_5m)
  if(sync_reset_uf_in)
    begin	
    temp_byte <= `BYTE_INITIAL_VALUE;
    saved <= `LOW;
    end
    else 
      if(mmc_enable)
        begin
        if(read_strobe) 
  	  begin
          temp_byte <= data_uf_in;
  	  saved <= read_strobe;
	  end
	  else if(receive_temp) saved <= !receive_temp;
                 else begin
                      temp_byte <= temp_byte;
                      saved <= saved;
                      end
        end
        else begin
             temp_byte <= temp_byte;
             saved <= saved;
             end

always @(negedge clock_5m)
  if(sync_reset_uf_in) transmit_byte <= `BYTE_INITIAL_VALUE;
    else if(saved) transmit_byte <= temp_byte;
           else if(data_transmit) transmit_byte <= transmit_byte << `HIGH;
                  else transmit_byte <= transmit_byte;

always @(negedge clock_5m)
  if(sync_reset_uf_in)
    begin	
    byte_counter <= `BYTE_COUNT_INITIAL;
    receive_temp <= `LOW;
    end
    else
      begin
      receive_temp <= saved;
      if(saved) byte_counter <= byte_counter + `HIGH;
        else if(last_transaction) byte_counter <= `BYTE_COUNT_INITIAL;
//        else if(transmit_done) byte_counter <= `BYTE_COUNT_INITIAL;
               else byte_counter <= byte_counter;
      end

assign gen_temp = (bit_counter == `GEN_TRANSMIT);

always @(negedge clock_5m)
  if(sync_reset_uf_in) data_transmit <= `LOW;
    else if(receive_temp) data_transmit <= receive_temp;
           else if(gen_temp) data_transmit <= ~gen_temp;
                  else data_transmit <= data_transmit;

always @(negedge clock_5m)
  if(sync_reset_uf_in) bit_counter <= `BIT_COUNT_INITIAL;
    else if(data_transmit) bit_counter <= bit_counter - `HIGH;
           else bit_counter <= {`LEN_BIT_COUNT{data_transmit}};

assign dat_fc_out = transmit_byte[`BYTE];

always @(negedge clock_5m)
  if(sync_reset_uf_in) transmit_done <= `HIGH;
    else if(mmc_enable) 
           begin
           if(last_transaction) transmit_done <= last_transaction;
             else if(ready_uf_in) transmit_done <= ~ready_uf_in;
                    else transmit_done <= transmit_done;
           end
           else transmit_done <= transmit_done;

endmodule