transmit.v

实现USB接口功能的VHDL和verilog完整源代码

/*
# --------------------------------------------------------------------------
#    Module      : transmit.v 
#     
#    Revision     : $Revision: 1.21 $
#    
#---------------------------------------------------------------------------
#   Purpose : UNIT to transmit MMC command or data to card.
#-------------------------------------------------------------------------
*/

`include "usbmmc_variable.v"

module transmit	( 
                // input
                mmc_enable,
//                usb_clock_uf_in,
                clock_5m,
                sync_reset_uf_in,

                cmdrdready_uf_in,
                cmdrddata_uf_in,

                endp1rdready_uf_in,
                endp1rddata_uf_in,

//                busy,

//                data_uf_in,
//                number_of_byte,

                // output
                cmdrd_fu_out,
                cmdrddatadone_fu_out,

                endp1rd_fu_out,
                endp1rddatadone_fu_out,

//                start_status,
                statuswrdatadone_fu_out,
                transmit,
                data_fc_out,
                pre_transmit
                );
	
input                   mmc_enable;
//input                   usb_clock_uf_in;
input                   clock_5m;
input                   sync_reset_uf_in;

input                   cmdrdready_uf_in;
input   [`BYTE:`LSB]    cmdrddata_uf_in;

input                   endp1rdready_uf_in;
input   [`BYTE:`LSB]    endp1rddata_uf_in;
input                   statuswrdatadone_fu_out;

//input                   busy;
//input   [`BYTE:`LSB]    number_of_byte;

output                  cmdrd_fu_out;
output                  cmdrddatadone_fu_out;

output                  endp1rd_fu_out;
output                  endp1rddatadone_fu_out;
//output                  start_status;
output                  transmit;
output                  data_fc_out;
output                  pre_transmit;

reg                     read_strobe;
reg     [`BYTE:`LSB]    transmit_byte;
reg     [`BYTE:`LSB]    temp_byte;
reg     [`BYTE:`LSB]    byte_counter;
reg                     data_fc_out;
reg     [`FOUR:`LSB]    bit_counter;
reg                     receive_temp;
reg                     saved;
reg                     transmit;
reg                     lock;
//reg     [`TWO:`LSB]     lock_count;
reg                     transmit_done;
reg     [`FIVE:`LSB]    pre_counter;
reg                     pre_transmit;
reg                     start_ready;
reg                     cmdrddatadone_fu_out;
reg                     endp1rddatadone_fu_out;
reg                     mode;
reg     [`BYTE:`LSB]    number_of_byte;
reg     [`BYTE:`LSB]    number_of_byte1;
reg     [`TWO:`LSB]     dummy_count;

wire    [`BYTE:`LSB]    data_uf_in;
wire                    last_transaction;
wire                    dummy;
wire                    gen_rd_strobe;
wire                    lock_tem;
//wire                    start_lock_count;
wire                    gen_temp;
wire                    ready_uf_in;
//wire    [`BYTE:`LSB]    number_of_byte;
wire                    cmdrd_fu_out;
wire                    endp1rd_fu_out;
//wire                    cmdrddatadone_fu_out;
//wire                    endp1rddatadone_fu_out;
wire                    real_ready;
wire                    gen_pre_transmit;
wire                    rel_pre_transmit;

//assign start_status = cmdrddatadone_fu_out;
assign ready_uf_in = (cmdrdready_uf_in)? cmdrdready_uf_in : 
                     (endp1rdready_uf_in)? endp1rdready_uf_in: `LOW;
assign data_uf_in = (cmdrdready_uf_in)? cmdrddata_uf_in : 
                     (endp1rdready_uf_in)? endp1rddata_uf_in: `DATA_INITIAL;

//always @(negedge clock_5m or posedge sync_reset_uf_in)
always @(negedge clock_5m)
  if(sync_reset_uf_in) number_of_byte <= `BYTE_INITIAL_VALUE;
    else number_of_byte <= (cmdrdready_uf_in)? `SIX :
                          (endp1rdready_uf_in)? `THIRTY_TWO: `ONE;

//always @(negedge clock_5m or posedge sync_reset_uf_in)
always @(negedge clock_5m)
  if(sync_reset_uf_in) number_of_byte1 <= `BYTE_INITIAL_VALUE;
    else number_of_byte1 <= number_of_byte;

assign cmdrd_fu_out = (cmdrdready_uf_in)? read_strobe : `LOW;
assign endp1rd_fu_out = (endp1rdready_uf_in)? read_strobe : `LOW;
//assign cmdrddatadone_fu_out=transmit_done;
//assign endp1rddatadone_fu_out=transmit_done;

//always @(negedge clock_5m or posedge sync_reset_uf_in)
always @(negedge clock_5m)
  if(sync_reset_uf_in) pre_counter <= `PRE_COUNT_INITIAL;
    else if(!cmdrdready_uf_in) pre_counter <= `PRE_COUNT_INITIAL;
           else if(!pre_counter[`FIVE] | (pre_counter[`FIVE] & !pre_counter[`LSB])) pre_counter <= pre_counter + `HIGH;

assign gen_pre_transmit = pre_counter == `START_DUMMY_CLOCK;
assign rel_pre_transmit = pre_counter == `END_DUMMY_CLOCK;
//always @(negedge clock_5m or posedge sync_reset_uf_in)
always @(negedge clock_5m)
  if(sync_reset_uf_in) pre_transmit <= `LOW;
    else if(gen_pre_transmit) pre_transmit <= gen_pre_transmit;
           else if(rel_pre_transmit) pre_transmit <= !rel_pre_transmit;

//always @(posedge usb_clock_uf_in or posedge sync_reset_uf_in)
always @(posedge clock_5m)
  if(sync_reset_uf_in) start_ready <= `LOW;
    else if(mmc_enable & rel_pre_transmit) start_ready <= rel_pre_transmit;
           else if(mmc_enable & transmit_done) start_ready <= !transmit_done;

assign real_ready = (cmdrdready_uf_in)? start_ready : `HIGH;
assign dummy = (endp1rdready_uf_in)? dummy_count[`TWO]: !dummy_count[`LSB];
//assign gen_rd_strobe = !busy & ready_uf_in & lock & !transmit_done & real_ready;
assign gen_rd_strobe = ready_uf_in & lock & !transmit_done & real_ready & dummy;

//always @(negedge clock_5m or posedge sync_reset_uf_in)
always @(negedge clock_5m)
  if(sync_reset_uf_in) dummy_count <= `DUMMY_COUNT_INITIAL;
    else if(!endp1rdready_uf_in) dummy_count <= `DUMMY_COUNT_INITIAL;
           else if(!dummy_count[`TWO]) dummy_count <= dummy_count + `HIGH;

//always @(posedge usb_clock_uf_in or posedge sync_reset_uf_in)
always @(posedge clock_5m)
  if(sync_reset_uf_in) read_strobe <= `LOW;
    else if(mmc_enable) read_strobe <= gen_rd_strobe;

//always @(posedge usb_clock_uf_in or posedge sync_reset_uf_in)
always @(posedge clock_5m)
  if(sync_reset_uf_in) mode <= `LOW;
    else if(read_strobe & mmc_enable) mode <= (cmdrdready_uf_in)? `CMD_MODE:
                                 (endp1rdready_uf_in)? `DATA_MODE: mode;

//always @(negedge usb_clock_uf_in or posedge sync_reset_uf_in)
always @(posedge clock_5m)
  if(sync_reset_uf_in) 
    begin
    cmdrddatadone_fu_out <= `LOW;
    endp1rddatadone_fu_out <= `LOW;
    end
    else if(mmc_enable) 
//           if(&byte_counter & (lock_count == `TWO))
           if(&byte_counter & lock_tem)
             case(mode)
               `CMD_MODE : cmdrddatadone_fu_out <= `HIGH;
               `DATA_MODE : endp1rddatadone_fu_out <= `HIGH;
             endcase
             else 
               begin
               if(statuswrdatadone_fu_out) cmdrddatadone_fu_out <= `LOW;
               if(ready_uf_in) endp1rddatadone_fu_out <= `LOW;
               end

//assign start_lock_count = (bit_counter == `GEN_LOCK) & !read_strobe;
//always @(posedge usb_clock_uf_in or posedge sync_reset_uf_in)
//always @(posedge clock_5m)
//  if(sync_reset_uf_in) lock_count <= `LOCK_COUNT_INITIAL;
//    else if(mmc_enable) 
//           if(start_lock_count) lock_count <= lock_count + `HIGH;
//             else lock_count <= {`LEN_LOCK_COUNT{start_lock_count}};

//assign lock_tem = (bit_counter == `GEN_LOCK) & !read_strobe & (lock_count == `LOCK_COUNT_TWO);
assign lock_tem = (bit_counter == `GEN_LOCK) & !read_strobe;
//always @(posedge usb_clock_uf_in or posedge sync_reset_uf_in)
always @(posedge clock_5m)
  if(sync_reset_uf_in) lock <= `HIGH;
    else if(mmc_enable) 
           if(gen_rd_strobe) lock <= ~gen_rd_strobe;
             else if(lock_tem) lock <= lock_tem;

assign	last_transaction = (byte_counter == number_of_byte1 );

//always @(posedge usb_clock_uf_in or posedge sync_reset_uf_in)
always @(posedge clock_5m)
  if(sync_reset_uf_in)
    begin	
    temp_byte <= `BYTE_INITIAL_VALUE;
    saved <= `LOW;
    end
    else 
      if(mmc_enable)
        if(read_strobe) 
  	  begin
          temp_byte <= data_uf_in;
  	  saved <= read_strobe;
	  end
	  else if(receive_temp) saved <= !receive_temp;

//always @(negedge clock_5m or posedge sync_reset_uf_in)
always @(negedge clock_5m)
  if(sync_reset_uf_in) transmit_byte <= `BYTE_INITIAL_VALUE;
    else if(saved) transmit_byte <= temp_byte;
           else if(transmit) transmit_byte <= transmit_byte << `HIGH;

//always @(negedge clock_5m or posedge sync_reset_uf_in)
always @(negedge clock_5m)
  if(sync_reset_uf_in)
    begin	
    byte_counter <= `BYTE_COUNT_INITIAL;
    receive_temp <= `LOW;
    end
    else
      begin
      receive_temp <= saved;
//      if(saved & |number_of_byte) byte_counter <= byte_counter + `HIGH;
      if(saved) byte_counter <= byte_counter + `HIGH;
        else if(transmit_done) byte_counter <= `BYTE_COUNT_INITIAL;
      end

assign gen_temp = (bit_counter == `GEN_TRANSMIT);
//always @(negedge clock_5m or posedge sync_reset_uf_in)
always @(negedge clock_5m)
  if(sync_reset_uf_in) transmit <= `LOW;
    else if(receive_temp) transmit <= receive_temp;
           else if(gen_temp) transmit <= ~gen_temp;

//always @(negedge clock_5m or posedge sync_reset_uf_in)
always @(negedge clock_5m)
  if(sync_reset_uf_in) bit_counter <= `BIT_COUNT_INITIAL;
    else if(transmit) bit_counter <= bit_counter - `HIGH;
           else bit_counter <= {`LEN_BIT_COUNT{transmit}};

//always @(negedge clock_5m or posedge sync_reset_uf_in)
always @(negedge clock_5m)
  if(sync_reset_uf_in) data_fc_out <= `DEFAULT_DATA_OUT;
    else if(transmit) data_fc_out <= transmit_byte[`BYTE];
           else data_fc_out	<= ~transmit;

//always @(negedge usb_clock_uf_in or posedge sync_reset_uf_in)
always @(negedge clock_5m)
  if(sync_reset_uf_in) transmit_done <= `HIGH;
    else if(mmc_enable) 
           if(last_transaction) transmit_done <= last_transaction;
             else if(ready_uf_in) transmit_done <= ~ready_uf_in;

endmodule