gen_clock_5m.v

来自「实现USB接口功能的VHDL和verilog完整源代码」· Verilog 代码 · 共 60 行

/*
# --------------------------------------------------------------------------
#    Module      : gen_clock_5m.v 
#     
#    Revision     : $Revision: 1.24 $
#    
#---------------------------------------------------------------------------
#   Purpose : Unit to generate 5m clock.
#-------------------------------------------------------------------------
*/

`include "usbmmc_variable.v"

module gen_clock_5m( 
                     usb_48_clock_uf_in,
                     usb_clock_uf_in,
                     divide_rate,
		     sync_reset_uf_in,
                     sync_reset_made,
		     clock_5m);

input		        usb_48_clock_uf_in;
input                   usb_clock_uf_in;
input   [`THREE:`LSB]   divide_rate;
input                   sync_reset_uf_in;
output                  sync_reset_made;
output                  clock_5m;

reg		clock_5m;
reg     [`SEVEN:`LSB] reset_count;
wire                 sync_reset_made;
reg     [`SEVEN:`LSB] count;


always @(posedge usb_48_clock_uf_in )
	if( sync_reset_uf_in) 
	   begin
		count <= `COUNT_INITIAL_VALUE;
                clock_5m <= `LOW;
	   end
	   else 
	      begin
                count <= count + `HIGH;
                case(divide_rate)
                  3'b011 : clock_5m <= count[`LSB];  // 24MHz
                  3'b010 : clock_5m <= count[`TWO];  // 12MHz
                  3'b001 : clock_5m <= count[`THREE]; // 6MHz
                  3'b000 : clock_5m <= count[`SEVEN]; // 400KHz
                  default : clock_5m <= count[`LSB];
                endcase
	      end
always @(posedge usb_clock_uf_in)
  if(sync_reset_uf_in) reset_count <= `RESET_COUNT_INITIAL;
    else if(!reset_count[`SEVEN]) reset_count <= reset_count + `HIGH;
           else reset_count <= reset_count;

assign sync_reset_made = !reset_count[`SEVEN];

endmodule