cmd_transmit.v

实现USB接口功能的VHDL和verilog完整源代码

/*
# --------------------------------------------------------------------------
#    Module      : cmd_transmit.v 
#     
#    Revision     : $Revision: 1.13 $
#    
#---------------------------------------------------------------------------
#   Purpose : UNIT to transmit MMC command or data to card.
#-------------------------------------------------------------------------
*/

`include "usbmmc_variable.v"

module cmd_transmit ( 
                // input
                mmc_enable,
                clock_5m,
                sync_reset_uf_in,
//                data_transmit_sync,
//                data_receive_sync,

                cmdrdready_uf_in,
                cmdrddata_uf_in,
                tmp_multi_getdata,

                // output
                cmdrd_fu_out,
                cmdrddatadone_fu_out,

                cmd_transmit,
                cmd_fc_out,
                cmd_pre_transmit
                );
	
input                   mmc_enable;
input                   clock_5m;
input                   sync_reset_uf_in;
//input                   data_receive_sync;
//input                   data_transmit_sync;

input                   cmdrdready_uf_in;
input   [`BYTE:`LSB]    cmdrddata_uf_in;
input                   tmp_multi_getdata;

output                  cmdrd_fu_out;
output                  cmdrddatadone_fu_out;

output                  cmd_transmit;
output                  cmd_fc_out;
output                  cmd_pre_transmit;

reg                     read_strobe;
reg     [`BYTE:`LSB]    transmit_byte;
reg     [`BYTE:`LSB]    temp_byte;
reg     [`BYTE:`LSB]    byte_counter;
reg     [`FOUR:`LSB]    bit_counter;
reg                     receive_temp;
reg                     saved;
reg                     cmd_transmit;
reg                     lock;
reg                     transmit_done;
reg     [`FIVE:`LSB]    pre_counter;
reg                     cmd_pre_transmit;
reg                     start_ready;
reg                     cmdrddatadone_fu_out;

wire                    cmd_fc_out;
wire    [`BYTE:`LSB]    number_of_byte1;
wire    [`BYTE:`LSB]    cmd_uf_in;
wire                    last_transaction;
wire                    gen_rd_strobe;
wire                    lock_tem;
wire                    gen_temp;
wire                    ready_uf_in;
wire                    cmdrd_fu_out;
wire                    real_ready;
wire                    gen_pre_transmit;
wire                    rel_pre_transmit;

//assign ready_uf_in = cmdrdready_uf_in & !data_transmit_sync & !data_receive_sync;
assign ready_uf_in = cmdrdready_uf_in && !tmp_multi_getdata;
assign cmd_uf_in = cmdrddata_uf_in;

assign number_of_byte1 = `SEVEN;

assign cmdrd_fu_out = read_strobe;

always @(negedge clock_5m)
  if(sync_reset_uf_in) pre_counter <= `PRE_COUNT_INITIAL;
    else if(!ready_uf_in) pre_counter <= `PRE_COUNT_INITIAL;
           else if(!pre_counter[`FIVE] | (pre_counter[`FIVE] & !pre_counter[`LSB])) pre_counter <= pre_counter + `HIGH;
                  else pre_counter <= pre_counter;

assign gen_pre_transmit = pre_counter == `START_DUMMY_CLOCK;
assign rel_pre_transmit = pre_counter == `END_DUMMY_CLOCK;

always @(negedge clock_5m)
  if(sync_reset_uf_in) cmd_pre_transmit <= `LOW;
    else if(gen_pre_transmit) cmd_pre_transmit <= gen_pre_transmit;
           else if(rel_pre_transmit) cmd_pre_transmit <= !rel_pre_transmit;
                  else cmd_pre_transmit <= cmd_pre_transmit;

always @(posedge clock_5m)
  if(sync_reset_uf_in) start_ready <= `LOW;
    else if(mmc_enable & rel_pre_transmit) start_ready <= rel_pre_transmit;
           else if(mmc_enable & transmit_done) start_ready <= !transmit_done;
                  else start_ready <= start_ready;

//assign real_ready = (cmdrdready_uf_in)? start_ready : `HIGH;
assign real_ready = (ready_uf_in)? start_ready : `HIGH;
assign gen_rd_strobe = ready_uf_in & lock & !transmit_done & real_ready;

always @(posedge clock_5m)
  if(sync_reset_uf_in) read_strobe <= `LOW;
    else if(mmc_enable) read_strobe <= gen_rd_strobe;
           else read_strobe <= read_strobe;

always @(posedge clock_5m)
  if(sync_reset_uf_in) cmdrddatadone_fu_out <= `HIGH;
    else if(mmc_enable) 
           begin
           if(&byte_counter & lock_tem) cmdrddatadone_fu_out <= `HIGH;
             else if(ready_uf_in) cmdrddatadone_fu_out <= `LOW;
                    else cmdrddatadone_fu_out <= cmdrddatadone_fu_out;
           end
           else cmdrddatadone_fu_out <= cmdrddatadone_fu_out;

assign lock_tem = (bit_counter == `GEN_LOCK) & !read_strobe;

always @(posedge clock_5m)
  if(sync_reset_uf_in) lock <= `HIGH;
    else if(mmc_enable) 
           begin
           if(gen_rd_strobe) lock <= ~gen_rd_strobe;
             else if(lock_tem) lock <= lock_tem;
                    else lock <= lock;
           end
           else lock <= lock;

assign	last_transaction = (byte_counter == number_of_byte1 );

always @(posedge clock_5m)
  if(sync_reset_uf_in)
    begin	
    temp_byte <= `BYTE_INITIAL_VALUE;
    saved <= `LOW;
    end
    else 
      if(mmc_enable)
        begin
        if(read_strobe) 
  	  begin
          temp_byte <= cmd_uf_in;
  	  saved <= read_strobe;
	  end
	  else if(receive_temp) saved <= !receive_temp;
                 else begin
                      temp_byte <= temp_byte;
                      saved <= saved;
                      end
        end
        else
          begin
          temp_byte <= temp_byte;
          saved <= saved;
          end

always @(negedge clock_5m)
  if(sync_reset_uf_in) transmit_byte <= `BYTE_INITIAL_VALUE;
    else if(saved) transmit_byte <= temp_byte;
           else if(cmd_transmit) transmit_byte <= transmit_byte << `HIGH;
                  else transmit_byte <= transmit_byte;

always @(negedge clock_5m)
  if(sync_reset_uf_in)
    begin	
    byte_counter <= `BYTE_COUNT_INITIAL;
    receive_temp <= `LOW;
    end
    else
      begin
      receive_temp <= saved;
      if(saved) byte_counter <= byte_counter + `HIGH;
        else if(transmit_done) byte_counter <= `BYTE_COUNT_INITIAL;
               else byte_counter <= byte_counter;
      end

assign gen_temp = (bit_counter == `GEN_TRANSMIT);

always @(negedge clock_5m)
  if(sync_reset_uf_in) cmd_transmit <= `LOW;
    else if(receive_temp) cmd_transmit <= receive_temp;
           else if(gen_temp) cmd_transmit <= ~gen_temp;
                  else cmd_transmit <= cmd_transmit;

always @(negedge clock_5m)
  if(sync_reset_uf_in) bit_counter <= `BIT_COUNT_INITIAL;
    else if(cmd_transmit) bit_counter <= bit_counter - `HIGH;
           else bit_counter <= {`LEN_BIT_COUNT{cmd_transmit}};

assign cmd_fc_out = transmit_byte[`BYTE];

always @(negedge clock_5m)
  if(sync_reset_uf_in) transmit_done <= `HIGH;
    else if(mmc_enable) 
           if(last_transaction) transmit_done <= last_transaction;
             else if(ready_uf_in) transmit_done <= ~ready_uf_in;
                    else transmit_done <= transmit_done;

endmodule