usiedcd.v

实现USB接口功能的VHDL和verilog完整源代码

                      databyte[6] <= databyte[6];
                      databyte[7] <= databyte[7];
                    end
                  3'b001 :
                    begin
                      databyte[0] <= databyte[0];
                      databyte[1] <= databit;
                      databyte[2] <= databyte[2];
                      databyte[3] <= databyte[3];
                      databyte[4] <= databyte[4];
                      databyte[5] <= databyte[5];
                      databyte[6] <= databyte[6];
                      databyte[7] <= databyte[7];
                    end
                  3'b010 :
                    begin
                      databyte[0] <= databyte[0];
                      databyte[1] <= databyte[1];
                      databyte[2] <= databit;
                      databyte[3] <= databyte[3];
                      databyte[4] <= databyte[4];
                      databyte[5] <= databyte[5];
                      databyte[6] <= databyte[6];
                      databyte[7] <= databyte[7];
                    end
                  3'b011 :
                    begin
                      databyte[0] <= databyte[0];
                      databyte[1] <= databyte[1];
                      databyte[2] <= databyte[2];
                      databyte[3] <= databit;
                      databyte[4] <= databyte[4];
                      databyte[5] <= databyte[5];
                      databyte[6] <= databyte[6];
                      databyte[7] <= databyte[7];
                    end
                  3'b100 :
                    begin
                      databyte[0] <= databyte[0];
                      databyte[1] <= databyte[1];
                      databyte[2] <= databyte[2];
                      databyte[3] <= databyte[3];
                      databyte[4] <= databit;
                      databyte[5] <= databyte[5];
                      databyte[6] <= databyte[6];
                      databyte[7] <= databyte[7];
                    end
                  3'b101 :
                    begin
                      databyte[0] <= databyte[0];
                      databyte[1] <= databyte[1];
                      databyte[2] <= databyte[2];
                      databyte[3] <= databyte[3];
                      databyte[4] <= databyte[4];
                      databyte[5] <= databit;
                      databyte[6] <= databyte[6];
                      databyte[7] <= databyte[7];
                    end
                  3'b110 :
                    begin
                      databyte[0] <= databyte[0];
                      databyte[1] <= databyte[1];
                      databyte[2] <= databyte[2];
                      databyte[3] <= databyte[3];
                      databyte[4] <= databyte[4];
                      databyte[5] <= databyte[5];
                      databyte[6] <= databit;
                      databyte[7] <= databyte[7];
                    end
                  3'b111 :
                    begin
                      databyte[0] <= databyte[0];
                      databyte[1] <= databyte[1];
                      databyte[2] <= databyte[2];
                      databyte[3] <= databyte[3];
                      databyte[4] <= databyte[4];
                      databyte[5] <= databyte[5];
                      databyte[6] <= databyte[6];
                      databyte[7] <= databit;
                    end
                endcase

	if (dcdst == DCDDATA && bitcount == 4'h7 && datavalid)		// loading last bit
		databytevalid <= 1'b1;
	else
		databytevalid <= 1'b0;

	if ((dcdst == DCDPID) && datavalid && (bitcount == 4'h7))
		checkpid <= 1'b1;
	else
		checkpid <= 1'b0;
		
	// generate single clock ticks for each packet startofframe
	if (usbreset)
		startofframe <= 1'b0;
	else if ((dcdst == DCDSOF) && datavalid && (bitcount == 4'ha))	// last bit of SOF
		startofframe <= 1'b1;
	else
		startofframe <= 1'b0;

	if (~datavalid)
		framenumber <= framenumber;
	else if (dcdst == DCDSOF)
		framenumber[bitcount[3:0]] <= databit;

	if (usbreset)
		rcvack <= 1'b0;
	else if (checkpid && ~badpid && (currentpid[3:0] == PIDACK))
		rcvack <= 1'b1;
	else
		rcvack <= 1'b0;
		
	if (usbreset)
		rcvdata <= 1'b0;
	else if (checkpid && ~badpid && ((currentpid[3:0] == PIDDATA0) || (currentpid[3:0] == PIDDATA1)))
		rcvdata <= 1'b1;
	else
		rcvdata <= 1'b0;
		
	if (usbreset)
		rcvdatain <= 1'b0;
	else if (checkpid && ~badpid && (currentpid[3:0] == PIDIN))
		rcvdatain <= 1'b1;
	else
		rcvdatain <= 1'b0;
		
	if (usbreset)
		rcvdataout <= 1'b0;
	else if (checkpid && ~badpid && (currentpid[3:0] == PIDOUT))
		rcvdataout <= 1'b1;
	else
		rcvdataout <= 1'b0;
		
	if (usbreset)
		rcvsetup <= 1'b0;
	else if (checkpid && ~badpid && (currentpid[3:0] == PIDSETUP))
		rcvsetup <= 1'b1;
	else
		rcvsetup <= 1'b0;
		
	if (dcdst == DCDDATA)
		rcvdatatogglebit <= currentpid[3];

				// must setup rcvcrc5data 1 tick ahead so it grabs data based on rcvcrc5data && datavalid
	if (nextdcdst == DCDADDR || nextdcdst == DCDENDP || nextdcdst == DCDSOF || nextdcdst == DCDCRC5)
		rcvcrc5data <= 1'b1;
	else
		rcvcrc5data <= 1'b0;

	if (dcdst == DCDCRC5 && datavalid && bitcount == 4'h4)	// last bit
		rcvcrc5check <= 1'b1;
	else
		rcvcrc5check <= 1'b0;
		
	if (dcdst == DCDDATA && nextdcdst == DCDEOP)	// works even if next to last clock is stuff (invalid)
		rcvcrc16check <= 1'b1;
	else
		rcvcrc16check <= 1'b0;
		
end
 
// state machine for decoding data from the usb
always @(posedge usbclock)
begin
	if (usbreset)
		dcdst <= DCDIDLE;
	else
		dcdst <= nextdcdst;
	prevdcdst <= dcdst;
end

always @(dcdst or usbreset or datavalid or databit or dataerror or dataidle or datase0 or 
		bitcount or currentpid or badpid or lookslikeasync)
begin
	if (usbreset)
	begin
		nextdcdst = DCDIDLE;
		resetbitcount = 1'b1;
	end
	else
		case (dcdst)	// synopsys parallel_case full_case
			DCDIDLE:
			begin
				if (dataidle || datase0 || ~datavalid)		// allow se0 due to reset OR 2-clock EOP
				begin
					resetbitcount = 1'b1;
					nextdcdst = DCDIDLE;
				end
				else if (dataerror)
				begin
					resetbitcount = 1'b1;
					nextdcdst = DCDERROR;
				end
				else 
				begin
					resetbitcount = 1'b0;		// start counting now, since first 0 is now
					nextdcdst = DCDSYNC;
				end
			end
			DCDSYNC:
			begin
				if (bitcount == 4'hf)
				begin
					resetbitcount = 1'b1;
					nextdcdst = DCDERROR;
				end
				else if (lookslikeasync)
				begin
					resetbitcount = 1'b1;
					nextdcdst = DCDPID;
                                end
				else
			        begin
					resetbitcount = 1'b0;
					nextdcdst = DCDSYNC;
				end
			end
			DCDPID:
			begin
				if (dataidle || dataerror || datase0)
				begin
					resetbitcount = 1'b1;
					nextdcdst = DCDERROR;
				end
				else if (datavalid && bitcount == 4'h7)	// last bit is a one
				begin
					resetbitcount = 1'b1;
					case (currentpid[3:0])	// synopsys full_case parallel_case
						PIDSOF: 	nextdcdst = DCDSOF;
						PIDOUT: 	nextdcdst = DCDADDR;
						PIDIN: 	nextdcdst = DCDADDR;
						PIDSETUP: 	nextdcdst = DCDADDR;
						PIDDATA0: 	nextdcdst = DCDDATA;
						PIDDATA1: 	nextdcdst = DCDDATA;
						PIDACK: 	nextdcdst = DCDEOP;
						PIDNAK: 	nextdcdst = DCDEOP;
						PIDSTALL: 	nextdcdst = DCDEOP;
						PIDPRE: 	nextdcdst = DCDEOP;  // JAKE 4.24		// go idle, we don't do slow
						default:	nextdcdst = DCDERROR;	// must have captured junk
					endcase
				end
				else 
				begin
					resetbitcount = 1'b0;
					nextdcdst = DCDPID;
				end
			end
			DCDADDR:
			begin
				if (dataidle || dataerror || datase0 || badpid)
				begin
					resetbitcount = 1'b1;
					nextdcdst = DCDERROR;
				end
				else if (datavalid && bitcount == 4'h6)	// last bit
				begin
					resetbitcount = 1'b1;
					nextdcdst = DCDENDP;
				end
				else 
				begin
					resetbitcount = 1'b0;
					nextdcdst = DCDADDR;
				end
			end
			DCDENDP:
			begin
				if (dataidle || dataerror || datase0)
				begin
					resetbitcount = 1'b1;
					nextdcdst = DCDERROR;
				end
				else if (datavalid && bitcount == 4'h3)	// last bit
				begin
					resetbitcount = 1'b1;
					nextdcdst = DCDCRC5;
				end
				else 
				begin
					resetbitcount = 1'b0;
					nextdcdst = DCDENDP;
				end
			end
			DCDSOF:
			begin
				if (dataidle || dataerror || datase0 || badpid)
				begin
					resetbitcount = 1'b1;
					nextdcdst = DCDERROR;
				end
				else if (datavalid && bitcount == 4'ha)	// last bit
				begin
					resetbitcount = 1'b1;
					nextdcdst = DCDCRC5;
				end
				else
				begin
					resetbitcount = 1'b0;
					nextdcdst = DCDSOF;
				end
			end
			DCDDATA:
			begin
				if (dataerror || badpid)
				begin
					resetbitcount = 1'b1;
					nextdcdst = DCDERROR;
				end
				else if (datase0)
				begin
					resetbitcount = 1'b1;
					nextdcdst = DCDEOP;
				end
				else if (datavalid && bitcount == 3'h7)
				begin
					resetbitcount = 1'b1;
					nextdcdst = DCDDATA;
				end
				else	// catch all for other error states
				begin
					resetbitcount = 1'b0;
					nextdcdst = DCDDATA;
				end
			end
			DCDCRC5:
			begin
				if (dataidle || dataerror || datase0)
				begin
					resetbitcount = 1'b1;
					nextdcdst = DCDERROR;
				end
				else if (datavalid && bitcount == 4'h4)	// last bit
				begin
					resetbitcount = 1'b1;
					nextdcdst = DCDEOP;
				end
				else 
				begin
					resetbitcount = 1'b0;
					nextdcdst = DCDCRC5;
				end
			end
			DCDEOP:
			begin
				resetbitcount = 1'b1;
				if (dataidle || dataerror || badpid)
					nextdcdst = DCDERROR;
				else if (~datavalid)		// could be stuff'd bit after crc5 or pid
					nextdcdst = DCDEOP;
				else if (datase0)	// last bit
					nextdcdst = DCDIDLE;
				else		// catch all error state - should have been se0, if not stuff'd or idle
					nextdcdst = DCDERROR;
			end
			DCDERROR:
			begin
				resetbitcount = 1'b1;
				if (dataidle || datase0)
					nextdcdst = DCDIDLE;
				else 
					nextdcdst = DCDERROR;
			end
	endcase
end

// make the ascii version of the dcd state
// synopsys translate_off
reg [8*10:1]	dcdstate;
always @(dcdst)
case (dcdst)
	DCDIDLE : dcdstate = "DCDIDLE";
	DCDSYNC : dcdstate = "DCDSYNC";
	DCDPID : dcdstate = "DCDPID";
	DCDSOF : dcdstate = "DCDSOF";
	DCDADDR : dcdstate = "DCDADDR";
	DCDENDP : dcdstate = "DCDENDP";
	DCDDATA : dcdstate = "DCDDATA";
	DCDCRC5 : dcdstate = "DCDCRC5";
	DCDERROR : dcdstate = "DCDERROR";
	DCDEOP : dcdstate = "DCDEOP";
endcase
// synopsys translate_on

endmodule