uusb_dual.v

实现USB接口功能的VHDL和verilog完整源代码

/*    
# --------------------------------------------------------------------------
#    Module      : Uusb_dual.v 
#     
#    Revision     : $Revision: 1.38 $
#    
#---------------------------------------------------------------------------
#   Purpose : 
#-------------------------------------------------------------------------
*/   

// FOR FPGA TEST TOP MODULE  

module Uusb_dual
	(
	// inputs from bus
		testmode,
		testreset,
		pwronresetb,
		clock48,	// 48 MHz clock
		rcvin,		// differential in
		vpin,		// plus in
		vmin,		// minus in
                // inputs from smart media
                card_ready,
                smart_rd_data,

		vmo,		// minus out
		vpo,		// plus out
		usboen,	// oe for usb bits
		suspend,
		usbclockout,
         gpiopin0,
		 gpiopin1,
		 gpiopin2,
		 gpiopin3,
		 gpiopin4,
		 gpiopin5,
		 gpiopin6,
		 gpiopin7,
		 disablebus,
		  // in /out for mmc
                dataout_dat_in,
                dataout_dat_out,
                dataout_dat_enable,

//                data_cf_in,
                //sm64_enable,
                clock_fc_out,

//                data_fc_out,
                datain_cmd_in,
                datain_cmd_out,
                datain_cmd_enable,
                // for MCU I/F
				data_out,
				data_in,
				clk_mcu,
                // outputs to smart media
                ale,
                cle,
                reb,
                web,
                wpb,
                out_enable,
                smart_wr_data

	);

input  testmode;
input  testreset;

  input      pwronresetb;
  input	     clock48;
  input	     rcvin;
  input	     vpin;
  input	     vmin;

  input      dataout_dat_in;
  output     dataout_dat_out;
  output     dataout_dat_enable;

  input              card_ready;
  //input              sm64_enable;
  input        [7:0] smart_rd_data;
  output     vmo;
  output     vpo;
  output     usboen;
  output     suspend;
  output     clock_fc_out;
  input      datain_cmd_in;
  output     datain_cmd_out;
  output     datain_cmd_enable;
  output     disablebus;
  output     usbclockout;
  output             ale;
  output             cle;
  output             reb;
  output             web;
  output             wpb;
  output             out_enable;
  output       [7:0] smart_wr_data;
  input     gpiopin0;
  input     gpiopin1;
  input     gpiopin2;

  output    gpiopin3;
  output    gpiopin4;
  output    gpiopin5;
  output    gpiopin6;
  output    gpiopin7;

  input   data_in;
  output  data_out;
  output  clk_mcu;
// wires for endpoints
  wire	     endp0rdstall = 1'b0;
  wire	     endp0wrstall = 1'b0;
  wire      endp3rdready = 1'b1;

  wire [7:0] currentalternatesetting;
  wire [7:0] endpwrdata;
  wire [7:0] endp2rddata;
  wire [7:0] endp3rddata;
  wire [7:0] endp0rddata;
  wire [6:0] devromdescriptorindex;
  wire [7:0] devromsetupaddr;
  wire [7:0] romdevsetupdata;
  wire [2:0] setupbyteaddr = 3'b000;
  wire [7:0] setupdataout;	// one of 8 bytes of the setup stage data
  wire[10:0] framenumber;
  wire[15:0] datawr3data;
  wire[2:0] clockrate;
 
   wire[2:0] setmode;

wire spimode = (setmode == 3'b001) ? 1'b1 : 1'b0;
wire enmmc   = (setmode == 3'b001 || setmode == 3'b010) ? 1'b1 : 1'b0;
wire disablebus =(setmode == 3'b000 || setmode == 3'b001) ? 1'b1 : 1'b0; 
wire sm64_enable  = (setmode == 3'b100) ? 1'b1 :1'b0;
wire sm_enable = (setmode == 3'b011 || setmode == 3'b100) ? 1'b1 : 1'b0;

/*
wire spimode =  1'b0;
wire enmmc   = 1'b1;
wire sm_enable   = 1'b0;
wire disablebus =  1'b0;
*/
wire busy_end_out;
wire busy_end_mmc = (enmmc && !spimode) ? busy_end_out:1'b1 ;
wire usbclock;
Ucore core (
        .testmode(testmode),
		.testreset(testreset),
		.clock48 (clock48),
        .rcvin (rcvin),
        .vpin (vpin),
        .vmin (vmin),
        .vmo (vmo),
        .vpo (vpo),
        .usboen (usboen),
        .usbclockout (usbclock),
        .usbclock (usbclock),
        .pwronreset(~pwronresetb),
    	.usbreset (usbreset),
    	.endpwrdata (endpwrdata),
    	.datapacketok (datapacketok),
    	.datapacketnotok (datapacketnotok),
        .devromdescriptorindex(devromdescriptorindex),
        .devromsetupaddr(devromsetupaddr),
        .romdevsetupdata(romdevsetupdata),
    	.romen(romen),
    	.endp0internaltogglebit(endp0internaltogglebit),
        .setupcycle(setupcycle),
        .setupbyteaddr(setupbyteaddr),
        .setupdata(setupdataout),
	    .rcvack(rcvack),
	    .suspend(suspend),
		.synthsof(synthsof),
	    .framenumber(framenumber),
	    .currentalternatesetting (currentalternatesetting),

        `include "Uvendorconnections.v"
 
	// connections to endpoint0 - read/write
	.endp0wr (endp0wr),
	.endp0wrready (endp0wrready),
	.endp0wrstall (endp0wrstall),
	.endp0rd (endp0rd),
	.endp0rddata (endp0rddata),
	//.endp0rdready (1'b1),
	.endp0rdready (endp0rdready && busy_end_mmc),
	.endp0rdstall (endp0rdstall),

	// connections to endpoint1 - write only
	.endp1wr (endp1wr),
	.endp1wrready (endp1wrready),
	//.endp1wrstall (endp1wrstall),

	// connections to endpoint2 - read only
	.endp2rd (endp2rd),
	.endp2rddata(endp2rddata),
	.endp2rdready(endp2rdready),
	//.endp2rdstall (endp2rdstall),
	
	.endp3rd (endp3rd),
	.endp3rddata(endp3rddata),
	.endp3rdready(endp3rdready)
	//.endp3rdstall (endp3rdstall)
	
	);
wire[7:0] datarddata;
wire[7:0] statusdatammc;
wire[7:0] statusdatasm;
wire[7:0] datawrdatammc;
wire[7:0] datawrdatasm;
wire[7:0] cmddatamc;
wire mcclock;
wire cmdrdmmc , cmdrdsm;
wire statuswrmmc, statuswrsm;
wire datardmmc,datardsm;
wire datawrmmc, datawrsm;
wire cmdrdmc = (enmmc) ? cmdrdmmc : cmdrdsm ;
wire statuswrmc =(enmmc)? statuswrmmc : statuswrsm ;
wire[7:0]  statusdatamc =(enmmc)? statusdatammc :statusdatasm;
wire datard = (enmmc) ? datardmmc :datardsm;
wire datawr = (enmmc) ? datawrmmc :datawrsm;
wire[7:0] datawrdata = (enmmc)? datawrdatammc :datawrdatasm;
wire clock_5m, sync_reset_made ;
//wire mcclock_out = (enmmc) ? clock_5m : usbclock ;// rha 12.23
//wire mcreset = (enmmc ) ? sync_reset_made : usbreset_d ;
wire mcreset = sync_reset_made ;

reg sofmmc;
always@(posedge mcclock)
 sofmmc <= synthsof;
wire getdataout = getdata || setcmdrd ;

UCtlreg ctlreg (
				.getbusy(getbusy),
				.getstatus(getstatus),
				.getstatuscheck(getstatuscheck),
				.usbclock(usbclock),
				.mcclock(mcclock),
				.syncreset(usbreset),
				.mcreset(mcreset),
				.datapacketok(datapacketok),
				.datapacketnotok(datapacketnotok),
				.cmdwrusb(endp0wr),
				.statusrdusb(endp0rd),
				.cmddatausb(endpwrdata),
				.statusdatausb(endp0rddata),
				.statusrdreadyusb(endp0rdready),
				.cmdwrreadyusb(endp0wrready),
                              // Memory Card
				.cmdrdmc(cmdrdmc),
				.cmddatamc(cmddatamc),
				.statuswrmc(statuswrmc),
				.statusdatamc(statusdatamc),
				.statuswrreadymc(statuswrreadymc),
				.cmdrdreadymc(cmdrdreadymc),
				// Configuration of MMC or SSFDC
				.enmmc(enmmc)//(enmmc)
				);
wire getstatusmmc = (cmdrdreadymc) ? 1'b0 : getstatus;
usbmmc u_usbmmc   (
				.getstatus_check(getstatuscheck),
				.busy_end_out(busy_end_out),
				.sof(sofmmc),
                .usb_48_clock_uf_in(clock48),
                .usb_clock_uf_in(usbclock),
                .mmc_enable(enmmc),
                //.disablebus(disablebus),
                .spimode(spimode),
                .divide_rate(clockrate),
                .sync_reset_uf_in(usbreset),
                //.clock_5m_out(clock_5m), //rha 12.23 
                //.clock_5m(mcclock), //rha 12.23
                .clock_5m_out(mcclock), // rha 12.24 temp
                .clock_5m(mcclock),// rha 12.24 temp
                .sync_reset_made(sync_reset_made),
                //.sync_reset_made(mcreset),
                .dataout_dat_in(dataout_dat_in),
                .dataout_dat_out(dataout_dat_out),
                .dataout_dat_enable(dataout_dat_enable),

                .getstatus(getstatusmmc),
                .getdata(getdataout),

                .cmdrdready_uf_in(cmdrdreadymc),
                .cmdrddata_uf_in(cmddatamc),

                .endp1rdready_uf_in(datardready),
                .endp1rddata_uf_in(datarddata),

                .statuswrready_uf_in(statuswrreadymc),
                .endp2wrready_uf_in(datawrready),

                .cmdrd_fu_out(cmdrdmmc),
                .cmdrddatadone_fu_out(cmddatadone),

                .statuswr_fu_out(statuswrmmc),
                .statuswrdata_fu_out(statusdatammc),
                .statuswrdatadone_fu_out(statuswrdone),

                .endp1rd_fu_out(datardmmc),
                .endp1rddatadone_fu_out(datarddone),

                .endp2wr_fu_out(datawrmmc),
                .endp2wrdata_fu_out(datawrdatammc),
                .endp2wrdatadone_fu_out(datawrdone),

                .setcmdwr(setcmdwr),
                .data_in(data_in),
		.data_out(data_out),
		.clk_mcu(clk_mcu),
				.clock_fc_out(clock_fc_out),
                .datain_cmd_in(datain_cmd_in),
                .datain_cmd_out(datain_cmd_out),
                .datain_cmd_enable(datain_cmd_enable),
                .endp3(datawr3data)
                );
wire[7:0] smart_rd_data;
wire[7:0] smart_wr_data;

smarti_box      u_smarti(
           //..mcclock(usbclock),
           //.mcreset(usbreset),
           .mcclock(mcclock),
           .mcreset(mcreset),
           .sm_enable(sm_enable),
	   .sm64_enable(sm64_enable),
           .disablebus(disablebus),
           .cmdrdready(cmdrdreadymc),
           .statuswrready(statuswrreadymc),
           .getbusy(getbusy),
           .getstatus(getstatus),
           .getdata(getdataout),
           .datardready(datardready),
           .datawrready(datawrready),
           .cmddata(cmddatamc),
           .datarddata(datarddata),
           .card_ready(card_ready),
           .smart_rd_data(smart_rd_data),

           .cmdrd(cmdrdsm),
           .statuswr(statuswrsm),
           .statusdata(statusdatasm),
           .datard(datardsm),
           .datawr(datawrsm),
           .datawrdata(datawrdatasm),
           .web(web),
           .reb(reb),
           .cle(cle),
           .ale(ale),
           //.wpb(wpb),
           .out_enable(out_enable),
           //.sm_state(sm_state), rha 11.29
           .smart_wr_data(smart_wr_data)
           );

wire[4:0] fifowraddr1;
wire[4:0] fifordaddr1;
wire[4:0] fifowraddr2;
wire[4:0] fifordaddr2;


Ufifocont endpoint1wr (
	  .usbclock(usbclock),
	  .mcclock(mcclock),
	  .syncreset(usbreset),
	  .mmcreset(mcreset),
   // To Fifo
	  .fifowraddr(fifowraddr1),
	  .fifordaddr(fifordaddr1),
   // write port USB
	  .fifowr(endp1wr),
	  .fifowrready(endp1wrready),
	  .datapacketok(datapacketok),
	  .datapacketnotok(datapacketnotok),
   // read port M/C 
	  .fiford(datard),   // 8051 make the read strobe for getting data
	  .fifordready(datardready)
	  );

Ufiforxcont endpoint2rd (
	  .getdata(getdataout),
	  .mcclock(mcclock),
	  .setcmdwr(setcmdwr),
	  .usbclock(usbclock),
	  .syncreset(usbreset),
	  .mmcreset(mcreset),
   // To fifo
	  .fifowraddr(fifowraddr2),
	  .fifordaddr(fifordaddr2),
   // write port  M/C
	  .fifowr(datawr),
	  .fifowrready(datawrready),
	  .datapacketok(datapacketok),
	  .datapacketnotok(datapacketnotok),
   // read port  USB
	  .fiford(endp2rd),
	  .fifordready(endp2rdready)
	  );

/*
Ufifo3rd endpoint3rd(
	   .usbclock(usbclock),
	   .syncreset(usbreset),
	   .fiford(endp3rd),
	   .fifowrdata(datawr3data),
	   .fiforddata(endp3rddata)
	   );
	   */

Udualfifo memtx(
			.waddr(fifowraddr1),
			.datain(endpwrdata),
			.clk(usbclock),
			.wren(endp1wr),
			.raddr(fifordaddr1), 
			.dataout(datarddata)
			);
Udualfiforx  memrx(
			.waddr(fifowraddr2),
			.datain(datawrdata),
			.clk(mcclock),
			.wren(datawr),
			.raddr(fifordaddr2),
			.dataout(endp2rddata)
			);

Udevrom rom (
	// addressing
	.devromdescriptorindex (devromdescriptorindex),
	.devromsetupaddr (devromsetupaddr),

	// read port
	.romdevsetupdata (romdevsetupdata)
	);


	       
endmodule