usienrzi.v

实现USB接口功能的VHDL和verilog完整源代码

/******************************************
	Filename: 	sienrzi.v 1.13
******************************************/

/*
The nrzi module extracts the data from the nrzi encoded data
and removes the bit stuffed bits.  It ignores data when we
are transmitting.  That's all!
*/
module Usienrzi
	(
	// inputs
		usbclock,
		syncreset,
		syncidle,
		syncrcv,
		syncse0,
		syncerror,
		xmitactive,

	// outputs
		databit,
		datavalid,
		dataidle,
		dataerror,
		datase0
	);

`include "Usienrzidef.v"

input	usbclock;
input	syncreset;	// synopsys sync_set_reset "syncreset"
input	syncidle;
input	syncrcv;
input	syncse0;
input	syncerror;
input	xmitactive;

output	databit;
output	datavalid;
output	dataerror;
output	dataidle;
output	datase0;

reg	datavalid;
reg	databit;
reg	dataidle;
reg	dataerror;
reg	datase0;

reg	[3:0]	nrzist, nextnrzist;
reg	syncrcvprev;
reg	validbit;

wire	nrzizero = syncrcvprev != syncrcv;

always @(posedge usbclock)
begin
	syncrcvprev <= syncrcv;	// get previous so I can find transitions
	if (validbit)
		databit <= !nrzizero;
	else
		databit <= databit;
	datavalid <= validbit;	// nice and clean output
	dataidle <= (nextnrzist == NRZIIDLE);
	dataerror <= ((nextnrzist == NRZIBAD) || (nextnrzist == NRZIERROR));
	datase0 <= syncse0;
end

// state machine for syncing to the rcv transition edges

always @(posedge usbclock)
begin
	if (syncreset)
		nrzist <= NRZIIDLE;
	else
		nrzist <= nextnrzist;
end

always @(nrzist or syncreset or syncidle or syncse0 or syncerror or nrzizero or xmitactive)
begin
	if (syncreset)
	begin
		nextnrzist = NRZIIDLE;
		validbit = 1'b0;
	end
	else
		case (nrzist)	// synopsys  parallel_case full_case
			NRZIIDLE:
			begin
				if (syncidle || syncse0 || xmitactive)
				begin
					nextnrzist = NRZIIDLE;
					validbit = 1'b0;
				end
				else
				begin
					nextnrzist = NRZIONE0;
					validbit = 1'b1;
				end
			end
			NRZIONE0:
			begin
				if (syncerror)
				begin
					validbit = 1'b0;
					nextnrzist = NRZIERROR;
				end
				else if (syncidle)
				begin
					validbit = 1'b0;
					nextnrzist = NRZIIDLE;
				end
				else if (syncse0)
				begin
					validbit = 1'b1;
					nextnrzist = NRZIONE0;
				end
				else if (nrzizero)
				begin
					validbit = 1'b1;
					nextnrzist = NRZIONE0;	// must have been a 0
				end
				else
				begin
					validbit = 1'b1;
					nextnrzist = NRZIONE1;	// must have been a 1
				end
			end
			NRZIONE1:
			begin
				if (syncerror)
				begin
					validbit = 1'b0;
					nextnrzist = NRZIERROR;
				end
				else if (syncidle)
				begin
					validbit = 1'b0;
					nextnrzist = NRZIIDLE;
				end
				else if (syncse0)
				begin
					validbit = 1'b1;
					nextnrzist = NRZIONE0;
				end
				else if (nrzizero)
				begin
					validbit = 1'b1;
					nextnrzist = NRZIONE0;	// must have been a 0
				end
				else
				begin
					validbit = 1'b1;
					nextnrzist = NRZIONE2;	// must have been a 1
				end
			end
			NRZIONE2:
			begin
				if (syncerror)
				begin
					validbit = 1'b0;
					nextnrzist = NRZIERROR;
				end
				else if (syncidle)
				begin
					validbit = 1'b0;
					nextnrzist = NRZIIDLE;
				end
				else if (syncse0)
				begin
					validbit = 1'b1;
					nextnrzist = NRZIONE0;
				end
				else if (nrzizero)
				begin
					validbit = 1'b1;
					nextnrzist = NRZIONE0;	// must have been a 0
				end
				else
				begin
					validbit = 1'b1;
					nextnrzist = NRZIONE3;	// must have been a 1
				end
			end
			NRZIONE3:
			begin
				if (syncerror)
				begin
					validbit = 1'b0;
					nextnrzist = NRZIERROR;
				end
				else if (syncidle)
				begin
					validbit = 1'b0;
					nextnrzist = NRZIIDLE;
				end
				else if (syncse0)
				begin
					validbit = 1'b1;
					nextnrzist = NRZIONE0;
				end
				else if (nrzizero)
				begin
					validbit = 1'b1;
					nextnrzist = NRZIONE0;	// must have been a 0
				end
				else
				begin
					validbit = 1'b1;
					nextnrzist = NRZIONE4;	// must have been a 1
				end
			end
			NRZIONE4:
			begin
				if (syncerror)
				begin
					validbit = 1'b0;
					nextnrzist = NRZIERROR;
				end
				else if (syncidle)
				begin
					validbit = 1'b0;
					nextnrzist = NRZIIDLE;
				end
				else if (syncse0)
				begin
					validbit = 1'b1;
					nextnrzist = NRZIONE0;
				end
				else if (nrzizero)
				begin
					validbit = 1'b1;
					nextnrzist = NRZIONE0;	// must have been a 0
				end
				else
				begin
					validbit = 1'b1;
					nextnrzist = NRZIONE5;	// must have been a 1
				end
			end
			NRZIONE5:
			begin
				if (syncerror)
				begin
					validbit = 1'b0;
					nextnrzist = NRZIERROR;
				end
				else if (syncidle)
				begin
					validbit = 1'b0;
					nextnrzist = NRZIIDLE;
				end
				else if (syncse0)
				begin
					validbit = 1'b1;
					nextnrzist = NRZIONE0;
				end
				else if (nrzizero)
				begin
					validbit = 1'b1;
					nextnrzist = NRZIONE0;	// must have been a 0
				end
				else
				begin
					validbit = 1'b1;
					nextnrzist = NRZIONE6;	// must have been a 1
				end
			end
			NRZIONE6:
			begin
				if (syncerror)
				begin
					validbit = 1'b0;
					nextnrzist = NRZIERROR;
				end
				else if (nrzizero)
				begin
					validbit = 1'b0;
					nextnrzist = NRZISTUFF;	// mandatory transition
				end
				else					// anything but a 0 is bad, including idle and se0
				begin
					validbit = 1'b0;
					nextnrzist = NRZIBAD;	// missed a stuff, we are hosed
				end
			end
			NRZISTUFF:
			begin
				if (syncerror)
				begin
					validbit = 1'b0;
					nextnrzist = NRZIERROR;
				end
				else if (syncidle)
				begin
					validbit = 1'b0;
					nextnrzist = NRZIIDLE;
				end
				else if (syncse0)
				begin
					validbit = 1'b1;
					nextnrzist = NRZIONE0;
				end
				else if (nrzizero)
				begin
					validbit = 1'b1;
					nextnrzist = NRZIONE0;	// must have been a 0
				end
				else
				begin
					validbit = 1'b1;
					nextnrzist = NRZIONE1;	// must have been a 1
				end
			end
			NRZIBAD:
			begin
				validbit = 1'b0;
				if (syncerror)
					nextnrzist = NRZIERROR;
				else if (syncse0)
				begin
					nextnrzist = NRZIIDLE;
				end
				else if (syncidle)
					nextnrzist = NRZIIDLE;
				else
					nextnrzist = NRZIBAD;	// hang out here until host stops sending
			end
			NRZIERROR:
			begin
				validbit = 1'b0;
				if (syncerror)
					nextnrzist = NRZIERROR;
				else if (syncidle)
					nextnrzist = NRZIIDLE;
				else 
					nextnrzist = NRZIERROR;
			end
	endcase
end

// make the ascii version of the nrzi state
// synopsys translate_off
reg [8*10:1]	nrzistate;
always @(nrzist)
case (nrzist)
	NRZIIDLE : nrzistate = "NRZIIDLE";
	NRZIONE0 : nrzistate = "NRZIONE0";
	NRZIONE1 : nrzistate = "NRZIONE1";
	NRZIONE2 : nrzistate = "NRZIONE2";
	NRZIONE3 : nrzistate = "NRZIONE3";
	NRZIONE4 : nrzistate = "NRZIONE4";
	NRZIONE5 : nrzistate = "NRZIONE5";
	NRZIONE6 : nrzistate = "NRZIONE6";
	NRZISTUFF : nrzistate = "NRZISTUFF";
	NRZIBAD : nrzistate = "NRZIBAD";
	NRZIERROR : nrzistate = "NRZIERROR";
endcase
// synopsys translate_on

endmodule