mod6_divide.map.rpt

用VerilogHDL编写的

; Allow Any Shift Register Size For Recognition                      ; Off                ; Off                ;
; Maximum Number of M512 Memory Blocks                               ; Unlimited          ; Unlimited          ;
; Maximum Number of M4K Memory Blocks                                ; Unlimited          ; Unlimited          ;
; Maximum Number of M-RAM Memory Blocks                              ; Unlimited          ; Unlimited          ;
; Ignore translate_off and translate_on Synthesis Directives         ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                 ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                   ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                       ; Normal compilation ; Normal compilation ;
; HDL message level                                                  ; Level2             ; Level2             ;
+--------------------------------------------------------------------+--------------------+--------------------+


+-------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                  ;
+----------------------------------+-----------------+------------------------+-------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path              ;
+----------------------------------+-----------------+------------------------+-------------------------------------------+
; mod6_divide.v                    ; yes             ; User Verilog HDL File  ; D:/job/practice/mod6_divide/mod6_divide.v ;
+----------------------------------+-----------------+------------------------+-------------------------------------------+


+------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary          ;
+---------------------------------------------+--------+
; Resource                                    ; Usage  ;
+---------------------------------------------+--------+
; Total logic elements                        ; 4      ;
;     -- Combinational with no register       ; 0      ;
;     -- Register only                        ; 0      ;
;     -- Combinational with a register        ; 4      ;
;                                             ;        ;
; Logic element usage by number of LUT inputs ;        ;
;     -- 4 input functions                    ; 0      ;
;     -- 3 input functions                    ; 3      ;
;     -- 2 input functions                    ; 0      ;
;     -- 1 input functions                    ; 1      ;
;     -- 0 input functions                    ; 0      ;
;         -- Combinational cells for routing  ; 0      ;
;                                             ;        ;
; Logic elements by mode                      ;        ;
;     -- normal mode                          ; 4      ;
;     -- arithmetic mode                      ; 0      ;
;     -- qfbk mode                            ; 0      ;
;     -- register cascade mode                ; 0      ;
;     -- synchronous clear/load mode          ; 0      ;
;     -- asynchronous clear/load mode         ; 4      ;
;                                             ;        ;
; Total registers                             ; 4      ;
; I/O pins                                    ; 3      ;
; Maximum fan-out node                        ; cnt[0] ;
; Maximum fan-out                             ; 4      ;
; Total fan-out                               ; 19     ;
; Average fan-out                             ; 2.71   ;
+---------------------------------------------+--------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                             ;
+----------------------------+-------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; M512s ; M4Ks ; M-RAMs ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |mod6_divide               ; 4 (4)       ; 4            ; 0           ; 0     ; 0    ; 0      ; 0            ; 0       ; 0         ; 0         ; 3    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (4)            ; 0 (0)           ; 0 (0)      ; |mod6_divide        ;
+----------------------------+-------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 4     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 4     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Thu Nov 02 14:00:35 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off mod6_divide -c mod6_divide
Warning (10238): Verilog Module Declaration warning at mod6_divide.v(7): ignored anonymous port(s) indicated by duplicate or dangling comma(s) in the port list for module "mod6_divide"
Info: Found 1 design units, including 1 entities, in source file mod6_divide.v
    Info: Found entity 1: mod6_divide
Info: Elaborating entity "mod6_divide" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at mod6_divide.v(20): truncated value with size 32 to match size of target (3)
Info: Implemented 7 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 1 output pins
    Info: Implemented 4 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
    Info: Processing ended: Thu Nov 02 14:00:36 2006
    Info: Elapsed time: 00:00:02