mod6_divide.v

来自「用VerilogHDL编写的」· Verilog 代码 · 共 32 行

module mod6_divide(
					//input
					clk,
					rst_n,
					//output
					clk_divide,
					);
				input clk;
				input rst_n;
				output clk_divide;
				reg    clk_divide;
				reg[2:0] cnt;
			always@(posedge clk or negedge rst_n)
			begin
				if(rst_n==1'b0)
					cnt<=3'b0;
				else if(cnt==3'b101)
					cnt<=3'b0;
				else
					cnt<=cnt+1;
				end
				
			always@(posedge clk or negedge rst_n)
			begin
				if(rst_n==1'b0)
					clk_divide<=1'b0;
				else if(cnt>2)
					clk_divide<=1'b1;
				else
					clk_divide<=1'b0;
			end
endmodule