calculat.bgn

verilog源码

Release 3.1i - Bitgen D.19
Copyright (c) 1995-2000 Xilinx, Inc.  All rights reserved.

Loading device database for application Bitgen from file "calculat.ncd".
   "calculat" is an NCD, version 2.32, device xc2s50, package pq208, speed -5
Loading device for application Bitgen from file 'v50.nph' in environment
E:/EDA/Xilinx.
Opened constraints file calculat.pcf.

Thu Oct 12 16:09:00 2006

bitgen -l -w -g ConfigRate:4 -g CclkPin:PULLUP -g TdoPin:PULLNONE -g M1Pin:PULLUP -g DonePin:PULLUP -g DriveDone:No -g StartUpClk:JTAGCLK -g DONE_cycle:4 -g GTS_cycle:5 -g GSR_cycle:6 -g M0Pin:PULLUP -g M2Pin:PULLUP -g ProgPin:PULLUP -g TckPin:PULLUP -g TdiPin:PULLUP -g TmsPin:PULLUP -g DonePipe:No -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:NONE -g Persist:Yes -m -g Readback calculat.ncd 

Running DRC.
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net U10/N14 is sourced
   by a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net U9/N14 is sourced by
   a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
DRC detected 0 errors and 2 warnings.
Saving ll file in "calculat.ll".
Creating bit map...
Saving bit stream in "calculat.bit".
Saving Readback bit file calculat.rbb.
Creating bit mask...
Saving mask bit stream in "calculat.msk".