calculat.par

verilog源码

Release 3.1i - Par D.19

Thu Oct 12 16:08:51 2006

par -w -ol 2 -d 0 map.ncd calculat.ncd calculat.pcf


Constraints file: calculat.pcf

Loading device database for application par from file "map.ncd".
   "calculat" is an NCD, version 2.32, device xc2s50, package pq208, speed -5
Loading device for application par from file 'v50.nph' in environment
E:/EDA/Xilinx.
Device speed data version:  ADVANCED 1.12 2000-05-03.


Resolved that IOB <$Net00083_> must be placed at site P34.
Resolved that IOB <C3> must be placed at site P129.
Resolved that GCLKIOB <10M> must be placed at site P80.
Resolved that IOB <$Net00005_> must be placed at site P122.
Resolved that IOB <C4> must be placed at site P132.
Resolved that IOB <$Net00006_> must be placed at site P121.
Resolved that IOB <C1> must be placed at site P125.
Resolved that IOB <$Net00066_> must be placed at site P15.
Resolved that IOB <$Net00007_> must be placed at site P120.
Resolved that IOB <RESET> must be placed at site P90.
Resolved that IOB <C2> must be placed at site P127.
Resolved that IOB <$Net00013_> must be placed at site P18.
Resolved that IOB <$Net00009_> must be placed at site P14.
Resolved that IOB <$Net00024_> must be placed at site P123.
Resolved that IOB <$Net00068_> must be placed at site P22.
Resolved that IOB <$Net00010_> must be placed at site P17.
Resolved that IOB <$Net00070_> must be placed at site P24.
Resolved that IOB <$Net00011_> must be placed at site P16.
Resolved that IOB <CARRY> must be placed at site P110.
Resolved that IOB <$Net00072_> must be placed at site P23.
Resolved that IOB <$Net00012_> must be placed at site P20.
Resolved that IOB <$Net00074_> must be placed at site P29.
Resolved that IOB <$Net00076_> must be placed at site P27.
Resolved that IOB <$Net00078_> must be placed at site P31.
Resolved that IOB <$Net00081_> must be placed at site P30.


Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            24 out of 140    17%

   Number of SLICEs                   70 out of 768     9%




Overall effort level (-ol):   2 (set by user)
Placer effort level (-pl):    2 (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    2 (set by user)

Starting the placer. REAL time: 0 secs 
Placement pass 1 ..............
Placer score = 26685
Optimizing ... 
Placer score = 24385
All IOBs have been constrained to specific sites.
Placer completed in real time: 0 secs 

Writing design to file "calculat.ncd".

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 0 secs 

0 connection(s) routed; 535 unrouted.
Starting router resource preassignment
Completed router resource preassignment. REAL time: 0 secs 
Starting iterative routing. 
Routing active signals.
.....
End of iteration 1 
535 successful; 0 unrouted; (0) REAL time: 0 secs 
Constraints are met. 
Total REAL time: 0 secs 
Total CPU  time: 0 secs 
End of route.  535 routed (100.00%); 0 unrouted.
No errors found. 
Completely routed. 

This design was run without timing constraints.  It is likely that much better
circuit performance can be obtained by trying either or both of the following:

  - Enabling the Delay Based Cleanup router pass, if not already enabled
  - Supplying timing constraints in the input design


Total REAL time to Router completion: 0 secs 
Total CPU time to Router completion: 1 secs 

Generating PAR statistics.

   The Delay Summary Report

   The Score for this design is: 274


The Number of signals not completely routed for this design is: 0

   The Average Connection Delay for this design is:        2.040 ns
   The Maximum Pin Delay is:                               5.233 ns
   The Average Connection Delay on the 10 Worst Nets is:   3.507 ns

   Listing Pin Delays by value: (ns)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 6.00  d >= 6.00
   ---------   ---------   ---------   ---------   ---------   ---------
          54         243         152          49          37           0

Writing design to file "calculat.ncd".


All signals are completely routed.

Total REAL time to PAR completion: 2 secs 
Total CPU time to PAR completion: 1 secs 

Placement: Completed - No errors found.
Routing: Completed - No errors found.

PAR done.