calculat.twr

来自「verilog源码」· TWR 代码 · 共 67 行

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Xilinx TRACE, Version D.19
Copyright (c) 1995-2000 Xilinx, Inc.  All rights reserved.

trce calculat.ncd calculat.pcf -e 3 -o calculat.twr

Design file:              calculat.ncd
Physical constraint file: calculat.pcf
Device,speed:             xc2s50,-5 (ADVANCED 1.12 2000-05-03)
Report level:             error report
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WARNING:Timing:2491 - No timing constraints found, doing default enumeration.

================================================================================
Timing constraint: Default period analysis
 1125 items analyzed, 0 timing errors detected.
 Minimum period is  16.994ns.
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================================================================================
Timing constraint: Default net enumeration
 136 items analyzed, 0 timing errors detected.
 Maximum net delay is   5.233ns.
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All constraints were met.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock to Setup on destination clock 10M
---------------+---------+---------+---------+---------+
               | Src/Dest| Src/Dest| Src/Dest| Src/Dest|
Source Clock   |Rise/Rise|Fall/Rise|Rise/Fall|Fall/Fall|
---------------+---------+---------+---------+---------+
10M            |    5.190|         |         |         |
---------------+---------+---------+---------+---------+


Timing summary:
---------------

Timing errors: 0  Score: 0

Constraints cover 1125 paths, 136 nets, and 535 connections (100.0% coverage)

Design statistics:
   Minimum period:  16.994ns (Maximum frequency:  58.844MHz)
   Maximum net delay:   5.233ns

WARNING:Timing - Clock nets using non-dedicated resources were found in this
   design. Clock skew on these resources will not be automatically addressed
   during path analysis. To create a timing report that analyzes clock skew for
   these paths, run trce with the '-skew' option.

   The following clock nets use non-dedicated resources:
      $Net00008_   U10/N14      U11/clkout1  U9/N14       $Net00016_   
      MOD          U11/clkout3  U11/clkout4  U11/clkout5  U11/clkout2  

Analysis completed Thu Oct 12 16:08:54 2006
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