ch10.18.htm

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<PRE><B>package</B> And_Pkg_Bad <B>is procedure</B> V_And(a, b : BIT; c: <B>out</B> BIT); <B>end</B>;
<B>package</B> <B>body</B> And_Pkg_Bad <B>is</B>
<B>procedure</B> V_And(a,b : BIT;c : <B>out</B> BIT) <B>is</B> <B>begin</B> c &lt;= a <B>and</B> b;<B>end</B>;
<B>end</B> And_Pkg_Bad;</PRE>

<P><P CLASS="ExerciseHead"><A NAME="pgfId=254170"></A>10.21&nbsp;(Type checking,
20 min.) Test the following code and explain the results:</P>

<PRE><B>type</B> T <B>is</B> INTEGER <B>range</B> 0 <B>to</B> 32; <B>variable</B> a: T;
a := (16 + 17) - 12; a := 16 - 12 + 17; a := 16 + (17 - 12);</PRE>

<P><P CLASS="ExerciseHead"><A NAME="pgfId=9839"></A>10.22&nbsp;(Debugging
VHDL code, 30 min.) Find and correct the errors in the following code. Create
a testbench for your code to check that it works correctly.</P>

<PRE><B>entity</B> UpDownCount_Bad <B>is </B>
<B>port</B>(clock, reset, up: STD_LOGIC; D: STD_LOGIC_VECTOR (7 <B>to</B> 0));
<B>end</B> UpDownCount_Bad;
<B>architecture</B> Behave <B>of</B> UpDownCount_Bad <B>is</B>
<B>begin</B> <B>process </B>(clock, reset, up); <B>begin</B> 
<B>if</B> (reset = '0') <B>then</B> D &lt;= '0000000'; 
<B>elseif</B> (rising_edge(clock)) <B>then</B>
<B>if </B>(up = 1) D &lt;= D+1; <B>else </B>D &lt;= D-1; <B>end</B> <B>if</B>;
<B>end</B> <B>if</B>; <B>end</B> <B>process</B>; <B>end</B> Behave;</PRE>

<P><P CLASS="ExerciseHead"><A NAME="pgfId=114228"></A>10.23&nbsp;(Subprograms,
20 min.) Write and test subprograms for these declarations:</P>

<PRE><B>function</B> Is_X_Zero (<B>signal</B> X : <B>in</B> BIT) <B>return</B> BIT;
<B>procedure</B> Is_A_Eq_B (<B>signal</B> A, B : BIT; <B>signal</B> Y : <B>out</B> BIT);</PRE>

<P><P CLASS="ExerciseHead"><A NAME="pgfId=367315"></A>10.24&nbsp;(Simulator
error messages, 10 min.) Analyze and attempt to simulate Arithmetic_2(Behave)
from Section&nbsp;10.12 and compare the error message you receive with that
from the MTI simulator (not all simulators are as informative). There are
no standards for error messages.</P>

<P><P CLASS="ExerciseHead"><A NAME="pgfId=340887"></A>10.25&nbsp;(Exhaustive
property of case statement, 30 min.) Write and simulate a testbench for
the state machine of Table&nbsp;10.8 and include your results. Is every
state transition tested by your program and is every transition covered
by an assignment statement in the code? (Hint: Think very carefully.) Repeat
this exercise for the state machine in Section&nbsp;10.10.6.</P>

<P><P CLASS="ExerciseHead"><A NAME="pgfId=178880"></A>10.26&nbsp;(Default
values for inputs, 20 min.) Replace the interface declaration for entity
Half_Adder in Section&nbsp;10.5 with the following (to remove the default
values):</P>

<PRE><B>port</B> (X, Y: <B>in</B> BIT ; Sum, Cout: <B>out</B> BIT);</PRE>

<P><P CLASS="Exercise"><A NAME="pgfId=122149"></A>Attempt to compile, elaborate,
and simulate configuration Simplest (the other entities needed, <CODE>AndGate</CODE>
and <CODE>XorGate</CODE> , must already be in<CODE> work </CODE>or in the
same file). You should get an error at some stage (different systems find
this error at different points--just because an entity compiles, that does
not mean it is error-free).</P>

<P><P CLASS="Exercise"><A NAME="pgfId=122132"></A>The LRM says &quot;...
A port of mode in may be unconnected ...only if its declaration includes
a default expression...&quot; [<A HREF="../../VHDL/LRM/HTML/1076_1.HTM#1.1.1.2">VHDL
93LRM1.1.1.2</A>].</P>

<P><P CLASS="Exercise"><A NAME="pgfId=122269"></A>We face a dilemma here.
If we do not drive inputs with test signals and leave an input port unconnected,
we can compile the model (since it is syntactically correct) but the model
is not semantically correct. On the other hand, if we give the inputs default
values, we might accidentally forget to make a connection and not notice.</P>

<P><P CLASS="ExerciseHead"><A NAME="pgfId=367604"></A>10.27&nbsp;(Adder
generation, 10 min.) Draw the schematic for Adder_1(Structure) of Section&nbsp;10.13.7,
labeling each instance with the VHDL instance name.</P>

<P><P CLASS="ExerciseHead"><A NAME="pgfId=367683"></A>10.28&nbsp;(Generate
statement, 20 min.) Draw a schematic corresponding to the following code
(label the cells with their instance names):</P>

<PRE>B1: <B>block</B> <B>begin </B>L1 : C <B>port</B> <B>map</B> (T, B, A(0), B(0)) ;
L2: <B>for</B> i <B>in</B> 1 <B>to</B> 3 <B>generate </B>L3 : <B>for</B> j <B>in</B> 1 <B>to</B> 3 <B>generate</B>
L4: <B>if</B> i+j &gt; 4 <B>generate </B>L5: C <B>port</B> <B>map</B> (A(i-1), B(j-1), A(i), B(j)) ;
<B>end</B> <B>generate</B>; <B>end</B> <B>generate</B>; <B>end</B> <B>generate</B>;
L6: <B>for</B> i <B>in</B> 1 <B>to</B> 3 <B>generate </B>L7: <B>for</B> j <B>in</B> 1 <B>to</B> 3 <B>generate</B>
L8: <B>if</B> i+j &lt; 4 <B>generate </B>L9: C <B>port</B> <B>map</B> (A(i+1), B(j+1), A(i), B(j)) ;
<B>end</B> <B>generate</B>; <B>end</B> <B>generate</B>; <B>end</B> <B>generate</B>;
<B>end</B> <B>block</B> B1;</PRE>

<P><P CLASS="Exercise"><A NAME="pgfId=245537"></A>Rewrite the code without
<CODE>generate</CODE> statements. How would you prove that your code really
is exactly equivalent to the original?</P>

<P><P CLASS="ExerciseHead"><A NAME="pgfId=241003"></A>10.29&nbsp;(Case statement,
20 min.) Create a package (<CODE> my_equal</CODE> ) that overloads the equality
operator so that <CODE>'X' = '0'</CODE> and <CODE>'X' = '1'</CODE> are both
<CODE>TRUE</CODE> . Test your package. Simulate the following design unit
and explain the result.</P>

<PRE><B>entity</B> Case_1 <B>is</B> <B>end</B>; <B>architecture</B> Behave <B>of</B> Case_1 <B>is</B>
<B>signal</B> r : BIT; <B>use</B> work.my_equal.<B>all</B>;
<B>begin</B> <B>process variable</B> twobit:STD_LOGIC_VECTOR(1 <B>to</B> 2); <B>begin</B> 
	twobit := &quot;X0&quot;;
	<B>case</B> twobit <B>is </B>
<B>		when</B> &quot;10&quot; =&gt; r &lt;= '1';
		<B>when</B> &quot;00&quot; =&gt; r &lt;= '1'; 
<B>		when others</B> =&gt; r &lt;= '0';
	<B>end</B> <B>case</B>; <B>wait</B>;
<B>end</B> <B>process</B>; <B>end</B>;</PRE>

<P><P CLASS="ExerciseHead"><A NAME="pgfId=367819"></A>10.30&nbsp;(State
machine) Create a testbench for the state machine of Section&nbsp;10.2.5.</P>

<P><P CLASS="ExerciseHead"><A NAME="pgfId=352313"></A>10.31&nbsp;(Mealy
state machine, 60 min.) Rewrite the state machine of Section&nbsp;10.2.5
as a Mealy state machine (the outputs depend on the inputs and on the current
state).</P>

<P><P CLASS="ExerciseHead"><A NAME="pgfId=133344"></A>10.32&nbsp;(Gate-level
D flip-flop, 30 min.) Draw the schematic for the following D flip-flop model.
Create a testbench (check for correct operation with combinations of <CODE>Clear</CODE>
, <CODE>Preset</CODE> , <CODE>Clock</CODE> , and <CODE>Data</CODE> ). Have
you covered all possible modes of operation? Justify your answer of yes
or no.</P>

<PRE><B>architecture</B> RTL <B>of</B> DFF_To_Test <B>is</B>
<B>signal</B> A, B, C, D, QI, QBarI : BIT; <B>begin</B> 
A &lt;= <B>not</B> (Preset <B>and</B> D <B>and</B> B) <B>after</B> 1 ns;
B &lt;= <B>not</B> (A <B>and</B> Clear <B>and</B> Clock) <B>after</B> 1 ns;
C &lt;= <B>not</B> (B <B>and</B> Clock <B>and</B> D) <B>after</B> 1 ns;
D &lt;= <B>not</B> (C <B>and</B> Clear <B>and</B> Data) <B>after</B> 1 ns;
QI &lt;= <B>not</B> (Preset <B>and</B> B <B>and</B> QBarI) <B>after</B> 1 ns;
QBarI &lt;= <B>not</B> (QI <B>and</B> Clear <B>and</B> C) <B>after</B> 1 ns;
Q &lt;= QI; QBar &lt;= QBarI;
<B>end</B>;</PRE>

<P><P CLASS="ExerciseHead"><A NAME="pgfId=352597"></A>10.33&nbsp;(Flip-flop
model, 20 min.) Add an asynchronous active-low preset to the D flip-flop
model of Table&nbsp;10.3. Generate a testbench that includes interaction
of the preset and clear inputs. What issue do you face and how did you solve
it?</P>

<P><P CLASS="ExerciseHead"><A NAME="pgfId=172846"></A>10.34&nbsp;(Register,
45 min.) Design a testbench for the register of Table&nbsp;10.4. Adapt the
8-bit register design to a 4-bit version with the following interface declaration:</P>

<PRE><B>entity</B> Reg4 <B>is</B> <B>port</B> (D : <B>in</B>  STD_LOGIC_VECTOR(7 <B>downto</B> 0);
Clk,Pre,Clr : <B>in</B> STD_LOGIC;Q,QB : <B>out</B> STD_LOGIC_VECTOR(7 <B>downto</B> 0));
<B>end</B> Reg8;</PRE>

<P><P CLASS="Exercise"><A NAME="pgfId=133429"></A>Create a testbench for
your 4-bit register with the following component declaration:</P>

<PRE><A NAME="pgfId=133432"></A> <B>component</B> DFF
<B>port</B>(Preset,Clear,Clock,Data:STD_LOGIC;Q,QBar:<B>out</B> STD_LOGIC_VECTOR);
<B>end</B> <B>component</B>;</PRE>

<P><P CLASS="ExerciseHead"><A NAME="pgfId=173239"></A>10.35&nbsp;(*Conversion
functions, 30 min.) Write a conversion function from <BR>
NATURAL to STD_LOGIC_VECTOR using the following declaration:</P>

<PRE><B>function</B> Convert (N, L: NATURAL) <B>return</B> STD_LOGIC_VECTOR;
-- N is NATURAL, L is length of STD_LOGIC_VECTOR</PRE>

<P><P CLASS="Exercise"><A NAME="pgfId=124248"></A>Write a similar conversion
function from STD_LOGIC_VECTOR to NATURAL:</P>

<PRE><B>function</B> Convert (B: STD_LOGIC_VECTOR) <B>return</B> NATURAL;</PRE>

<P><P CLASS="Exercise"><A NAME="pgfId=133519"></A>Create a testbench to
test your functions by including them in a package.</P>

<P><P CLASS="ExerciseHead"><A NAME="pgfId=123154"></A>10.36&nbsp;(Clock
procedure, 20 min.) Design a clock procedure for a two-phase clock (C1,
C2) with variable high times (<CODE> HT1</CODE> , <CODE>HT2</CODE> ) and
low times (<CODE> LT1</CODE> , <CODE>LT2</CODE> ) and the following interface.
Include your procedure in a package and write a model to test it.</P>

<PRE><B>procedure</B> Clock (C1, C2 : <B>out</B> STD_LOGIC; HT1, HT2, LT1, LT2 : TIME);</PRE>

<P><P CLASS="ExerciseHead"><A NAME="pgfId=124095"></A>10.37&nbsp;(Random
number, 20 min.) Design a testbench for the following procedure:</P>

<PRE><B>procedure</B> uniform (seed : <B>inout</B> INTEGER <B>range</B> 0 <B>to</B> 15) <B>is</B>
	<B>variable</B> x : INTEGER;
	<B>begin </B>x := (seed*11) + 7; seed := x <B>mod</B> 16;
<B>end</B> uniform;</PRE>

<P><P CLASS="ExerciseHead"><A NAME="pgfId=466602"></A>10.38&nbsp;(Full-adder,
30 min.) Design and test a behavioral model of a full adder with the following
interface:</P>

<PRE><B>entity</B> FA <B>is</B> <B>port</B> (X, Y, Cin : STD_LOGIC; Cout, Sum : <B>out</B> STD_LOGIC);
<B>end</B>;</PRE>

<P><P CLASS="Exercise"><A NAME="pgfId=367798"></A>Repeat the exercise for
inputs and outputs of type <CODE>UNSIGNED</CODE> .</P>

<P><P CLASS="ExerciseHead"><A NAME="pgfId=125518"></A>10.39&nbsp;(8-bit
adder testbench, 60 min.) Write out the code corresponding to the generate
statements of Adder_1 (<CODE> Structure</CODE> ) in Section&nbsp;10.13.7.
Write a testbench to check your adder. What problems do you encounter? How
thorough do you believe your tests are?</P>

<P><P CLASS="ExerciseHead"><A NAME="pgfId=122836"></A>10.40&nbsp;(Shift-register
testbench, 60 min.) Design a testbench for the shift register of Table&nbsp;10.4.
Convert this model to use <CODE>STD_LOGIC</CODE> types with the following
interface:</P>

<PRE><B>entity</B> ShiftN <B>is</B> 
<B>port</B> (CLK, CLR, LD, SH, DIR : STD_LOGIC; 
	D : STD_LOGIC_VECTOR; Q : <B>out</B> STD_LOGIC_VECTOR);
<B>end</B>;</PRE>

<P><P CLASS="ExerciseHead"><A NAME="pgfId=122540"></A>10.41&nbsp;(Multiplier,
60 min.) Design and test a multiplier with the following interface:</P>

<PRE><B>entity</B> Mult8 <B>is</B> 
<B>port</B> (A, B : STD_LOGIC_VECTOR(3 <B>downto</B> 0); 
Start, CLK, Reset : <B>in</B> STD_LOGIC;
Result : <B>out</B> STD_LOGIC_VECTOR(7 <B>downto</B> 0); Done : <B>out </B>BIT);
<B>end</B>;</PRE>

<P><P CLASS="ExercisePartFirst"><A NAME="pgfId=28202"></A>Create testbench
code to check your model.</P>

<P><P CLASS="ExercisePart"><A NAME="pgfId=28203"></A>Catalog each compile
step with the syntax errors as you debug your code.</P>

<P><P CLASS="ExercisePart"><A NAME="pgfId=28204"></A>Include a listing of
the first code you write together with the final version.</P>