ch10.18.htm
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<B>entity</B> prep3_1 <B>is</B> <B>port</B>(Clk, Reset: STD_LOGIC;
I : STD_LOGIC_VECTOR(7 <B>downto</B> 0); O : <B>out</B> STD_LOGIC_VECTOR(7 <B>downto</B> 0));
<B>end</B> prep3_1;
<B>architecture</B> Behave <B>of</B> prep3_1 <B>is</B>
<B>type</B> STATE_TYPE <B>is</B> (sX,s0,sa,sb,sc,sd,se,sf,sg);
<B>signal</B> state : STATE_TYPE; <B>signal</B> Oi : STD_LOGIC_VECTOR(7 <B>downto</B> 0);
<B>begin</B>
O <= Oi;
<B>process</B> (Reset, Clk) <B>begin</B>
<B>if</B> (Reset = '1') <B>then</B> state <= s0; Oi <= (<B>others</B> => '0');
<B>elsif</B> rising_edge(Clk) <B>then</B>
<B>case</B> state <B>is</B>
<B>when</B> s0 =>
<B>if</B> (I = X"3c") <B>then</B> state <= sa; Oi <= X"82";
<B>else</B> state <= s0; Oi <= (<B>others</B> => '0');
<B>end</B> <B>if</B>;
<B>when</B> sa =>
<B>if</B> (I = X"2A") <B>then</B> state <= sc; Oi <= X"40";
<B>elsif</B> (I = X"1F") <B>then</B> state <= sb; Oi <= X"20";
<B>else</B> state <= sa; Oi <= X"04";
<B>end</B> <B>if</B>;
<B>when</B> sb =>
<B>if</B> (I = X"AA") <B>then</B> state <= se; Oi <= X"11";
<B>else</B> state <= sf; Oi <= X"30";
<B>end</B> <B>if</B>;
<B>when</B> sc => state <= sd; Oi <= X"08";
<B>when</B> sd => state <= sg; Oi <= X"80";
<B>when</B> se => state <= s0; Oi <= X"40";
<B>when</B> sf => state <= sg; Oi <= X"02";
<B>when</B> sg => state <= s0; Oi <= X"01";
<B>when</B> <B>others</B> => state <= sX; Oi <= (<B>others</B> => 'X');
<B>end</B> <B>case</B>;
<B>end</B> <B>if</B>;
<B>end</B> <B>process</B>;
<B>end</B>;</PRE>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=20929"></A>10.60 (Edge detection,
30 min) Explain the construction of the IEEE 1164 function to detect the
rising edge of a signal, <CODE>rising_edge(s)</CODE> . List all the changes
in signal <CODE>s</CODE> that correspond to a rising edge.</P>
<PRE> <B>function</B> rising_edge (<B>signal</B> s : STD_ULOGIC) <B>return</B> BOOLEAN <B>is</B>
<B>begin</B> <B>return</B>
(s'EVENT <B>and</B> (To_X01(s) = '1') <B>and</B> (To_X01(s'LAST_VALUE) = '0')); <B>end</B>;</PRE>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=173517"></A>10.61 (*Real,
10 min.) Determine the smallest real in your VHDL environment.</P>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=20941"></A>10.62 (*Stop,
30 min.) How many ways are there to stop a VHDL simulator?</P>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=65270"></A>10.63 (*Arithmetic
package, 60 min.) Write a function for an arithmetic package to subtract
two's complement numbers. Create a test bench to check your function. Your
declarations in the package header should look like this:</P>
<PRE><B>type</B> TC <B>is</B> <B>array</B> (INTEGER <B>range</B> <>) <B>of</B> STD_LOGIC;
<B>function</B> "-"(L : TC; R : TC) <B>return</B> TC;</PRE>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=48575"></A>10.64 (***Reading
documentation, hours) There are a few gray areas in the interpretation of
the VHDL-87 LRM some of which were clarified in the VHDL-93 revision. One
VHDL system has a "compatibility mode" that allows alternative
interpretations. For each of the following "issues" taken from
the actual tool documentation try to interpret what was meant, determine
the interpretation taken by your own software, and then rewrite the explanation
clearly using examples.</P>
<P><P CLASS="ExercisePartFirst"><A NAME="pgfId=368647"></A>* "Unassociated
variable and signal parameters. Compatibility mode allows variable and signal
parameters to subprograms to be unassociated if they have a default value.
Otherwise, an error is generated."</P>
<P><P CLASS="Exercise"><A NAME="pgfId=368657"></A>Example answer: Consider
the following code:</P>
<PRE><B>package</B> Util_2 <B>is</B>
<B>procedure</B> C(<B>signal</B> Clk : <B>out</B> BIT; <B>signal</B> P : TIME := 10 ns);
<B>end</B> Util_2;
<B>package</B> <B>body</B> Util_2 <B>is</B>
<B>procedure</B> C(<B>signal</B> Clk : <B>out</B> BIT; <B>signal</B> P : TIME := 10 ns) <B>is</B>
<B>begin</B> <B>loop</B> Clk <= '1' <B>after</B> P/2, '0' <B>after</B> P;
<B>wait</B> <B>for</B> P; <B>end</B> <B>loop</B>; <B>end</B>; <B>end</B> Util_2;
<B>entity</B> Test_Compatibility_1 <B>is</B> <B>end</B>; <B>use</B> work.Util_2.<B>all</B>;
<B>architecture</B> Behave <B>of</B> Test_Compatibility_1 <B>is</B>
<B>signal</B> v,w,x,y,z : BIT; <B>signal</B> s : TIME := 5 ns;
<B>begin</B> <B>process</B> <B>variable</B> v : TIME := 5 ns; <B>begin</B>
C(v, s); -- parameter s is OK since P is declared as signal
-- C(w, v); -- would be OK if P is declared as variable instead
-- C(x, 5 ns); -- would be OK if P is declared as constant instead
-- C(y); -- unassociated, an error if P is signal or variable
-- C(z,<B>open</B>); -- open, an error if P is signal or variable
<B>end</B> <B>process</B>; <B>end</B>;</PRE>
<P><P CLASS="Exercise"><A NAME="pgfId=369423"></A>The Compass Scout simulator
(which does not have a compatibility mode) generates an error during analysis
if a signal or variable subprogram parameter is open or unassociated (a
constant subprogram parameter may be unassociated or open).</P>
<P><P CLASS="ExercisePart"><A NAME="pgfId=368623"></A>* "Allow <CODE>others</CODE>
in an aggregate within a record aggregate. The LRM [7.3.2.2] defines nine
situations where <CODE>others</CODE> may appear in an aggregate. In compatibility
mode, a tenth case is added. In this case, <CODE>others</CODE> is allowed
in an aggregate that appears as an element association in a record element."</P>
<P><P CLASS="ExercisePart"><A NAME="pgfId=368625"></A>* "<CODE> BIT'('1')</CODE>
parsed as <CODE>BIT ' ('1')</CODE> . The tick (<CODE> '</CODE>
) character is being used twice in this example. In the first case as an
attribute indicator, in the second case, to form a character literal. Without
the compatibility option, the analyzer adopts a strict interpretation of
the LRM, and without white space around the first tick, the fragment is
parsed as <CODE>BIT '('1')</CODE> , that is, the left parenthesis (<CODE>
'('</CODE> ) is the character literal."</P>
<P><P CLASS="ExercisePart"><A NAME="pgfId=368631"></A>** "Generate
statement declarative region. Generate statements form their own declarative
region. In compatibility mode, configuration specifications will apply to
items being instantiated within a generate statement."</P>
<P><P CLASS="ExercisePart"><A NAME="pgfId=368637"></A>** "Allow type
conversion functions on open parameters. If a parameter is specified as
open, it indicates a parameter without an explicit association. In such
cases, the presence of a type conversion function is meaningless. Compatibility
mode allows the type conversion functions."</P>
<P><P CLASS="ExercisePart"><A NAME="pgfId=48576"></A>*** "Entity class
flexibility. Section [3.1.2] of the LRM defines the process of creating
a new integer type. The type name given is actually assigned to a subtype
name, related to an anonymous base type. This implies that the entity class
used during an attribute specification [LRM 5.1] should indicate subtype,
rather than type. Because the supplied declaration was type rather than
subtype, compatibility mode allows type."</P>
<P><P CLASS="ExercisePart"><A NAME="pgfId=220993"></A>*** "Allowing
declarations beyond an all/others specification. Section [5.1] of the LRM
states that the first occurrence of the reserved word <CODE>all</CODE> or
<CODE>others</CODE> in an attribute specification terminates the declaration
of the related entity class. The LRM declares that the entity/architecture
and package/package body library units form single declaration regions [LRM
10.1] that are the concatenation of the two individual library declarative
regions. For example, if a signal attribute specification with <CODE>all</CODE>
or <CODE>others</CODE> was specified in the entity, it would be impossible
to declare a signal in the architecture. In compatibility mode, this LRM
limitation is removed."</P>
<P><P CLASS="ExercisePart"><A NAME="pgfId=48583"></A>*** "User-defined
attributes on overloaded functions. In compatibility mode, user-defined
attributes are allowed to be associated with overloaded functions. Note:
Even in compatibility mode, there is no way to retrieve the different attributes."</P>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=48631"></A>10.65 (*1076 interpretations,
30 min.) In a DAC paper, the author writes: `It was experienced that (company
R) might have interpreted IEEE 1076 differently than (company S) did, e.g.
concatenations (&) are not allowed in "case selector" expressions
for (company S).' Can you use concatenation in your VHDL tool for either
the <CODE>expression</CODE> or <CODE>choices</CODE> for a <CODE>case</CODE>
statement?</P>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=358615"></A>10.66 (**Interface
declarations, 15 min.) Analyze the following and comment:</P>
<PRE><B>entity</B> Interface_1 <B>is</B>
<B>generic</B> (I : INTEGER; J : INTEGER := I; K, L : INTEGER);
<B>port</B> (A : BIT_VECTOR; B : BIT_VECTOR(A'RANGE); C : BIT_VECTOR (K <B>to</B> L));
<B>procedure</B> X(P, Q : INTEGER; R : INTEGER <B>range</B> P <B>to</B> Q);
<B>procedure</B> Y(S : INTEGER <B>range</B> K <B>to</B> L);
<B>end</B> Interface_1;</PRE>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=88367"></A>10.67 (**Wait
statement, 10 min.) Construct the sensitivity set and thus the sensitivity
list for the following <CODE>wait</CODE> statement (that is, rewrite the
<CODE>wait</CODE> statement in the form <CODE>wait on sensitivity_list until
condition</CODE> ).</P>
<PRE><B>entity</B> Complex_Wait <B>is</B> <B>end</B>;
<B>architecture</B> Behave <B>of</B> Complex_Wait <B>is</B>
<B>type</B> A <B>is</B> <B>array</B> (1 <B>to</B> 5) <B>of</B> BOOLEAN;
<B>function</B> F (P : BOOLEAN) <B>return</B> BOOLEAN;
<B>signal</B> S : A; <B>signal</B> i, j : INTEGER <B>range</B> 1 <B>to</B> 5;
<B>begin</B> <B>process begin</B>
<B>wait</B> <B>until</B> F(S(3)) <B>and</B> (S(i) <B>or</B> S(j));
<B>end</B> <B>process</B>;
<B>end</B>;</PRE>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=60147"></A>10.68 (**Shared
variables, 20 min.) Investigate the following code and comment:</P>
<PRE><B>architecture</B> Behave <B>of</B> Shared_1 <B>is</B>
<B>subtype</B> S <B>is</B> INTEGER <B>range</B> 0 <B>to</B> 1; <B>shared</B> <B>variable</B> C : S := 0; <B>begin</B>
<B>process</B> <B>begin</B> C := C + 1; <B>wait</B>; <B>end</B> <B>process</B>;
<B>process</B> <B>begin</B> C := C - 1; <B>wait</B>; <B>end</B> <B>process</B>;
<B>end</B>;</PRE>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=189619"></A>10.69 (Undocumented
code and ranges, 20 min.) Explain the purpose of the following function
(part of a package from a well-known synthesis company) with a parameter
of type SIGNED. Write a testbench to check your explanation. Investigate
what happens when you call this function with a string-literal argument,
for example with the statement X <= IM("11100").
What is the problem and why does it happen? Rewrite the code, including
documentation, to avoid this problem.</P>
<PRE><B>type</B> SIGNED <B>is</B> <B>array</B> (NATURAL <B>range</B> <> ) <B>of</B> BIT;
<B>function</B> IM (L : SIGNED) <B>return</B> INTEGER <B>is</B> <B>variable</B> M : INTEGER;
<B>begin</B> M := L'RIGHT-1;
<B>for</B> i <B>in</B> L'LEFT-1 <B>downto</B> L'RIGHT <B>loop</B>
<B>if</B> (L(i) = (<B>not</B> L(L'LEFT))) <B>then</B> M := i; <B>exit</B>; <B>end</B> <B>if</B>;
<B>end</B> <B>loop</B>; <B>return</B> M;
<B>end</B>;</PRE>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=370779"></A>10.70 (Timing
parameters, 20 min.) Write a model and a testbench for a two-input AND gate
with separate rising (tpLH) and falling (tpHL) delays using the following
interface:</P>
<PRE><B>entity</B> And_Process <B>is</B>
<B>generic</B> (tpLH, tpHL : TIME); <B>port</B> (a, b : BIT; z : <B>out</B> BIT) <B>end</B>;</PRE>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=371478"></A>10.71 (Passive
code in entities, 30 min.) Write a procedure (CheckTiming, part of a package
<CODE>Timing_Pkg</CODE> ) to check that two timing parameters (tPLH and
tPHL) are both greater than zero. Include this procedure in a two-input
AND gate model (<CODE> And_Process</CODE> ). Write a testbench to show your
procedure and gate model both work. Rewrite the entity for <CODE>And_Process</CODE>
to include the timing check as part of the entity declaration. You are allowed
to include passive code (no assignments to signals and so on) directly in
each entity. This avoids having to include the timing checks in each architecture.</P>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=358489"></A>10.72 (Buried
code, 30 min.) Some companies bury instructions to the software within their
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