ch10.18.htm
来自「介绍asci设计的一本书」· HTM 代码 · 共 1,149 行 · 第 1/5 页
HTM
1,149 行
packages. Here is an example of part of the arithmetic package from an imaginary
company called SissyN:</P>
<PRE><B>function</B> UN_plus(A, B : UN) <B>return</B> UN <B>is</B>
<B>variable</B> CRY : STD_ULOGIC; <B>variable</B> X,SUM : UN (A'LEFT <B>downto</B> 0);
-- pragma map_to_operator ADD_UNS_OP
-- pragma type_function LEFT_UN_ARG
-- pragma return_port_name Z
<B>begin</B>
-- sissyn synthesis_off
<B>if</B> (A(A'LEFT) = 'X' <B>or</B> B(B'LEFT) = 'X') <B>then</B> SUM := (<B>others </B>=> 'X');
<B>return</B>(SUM);
<B>end</B> <B>if</B>;
-- sissyn synthesis_on
CRY := '0'; X := B;
<B>for</B> i <B>in</B> 0 <B>to</B> A'LEFT <B>loop</B>
SUM(i) := A(i) <B>xor</B> X(i) <B>xor</B> carry;
CRY := (A(i) <B>and</B> X(i)) <B>or</B> (A(i) <B>and</B> CRY) <B>or</B> (CRY <B>and</B> X(i));
<B>end</B> <B>loop</B>; <B>return</B> SUM;
<B>end</B>;</PRE>
<P><P CLASS="Exercise"><A NAME="pgfId=358553"></A>Explain what this function
does. Can you now hazard a guess at what each of the comments means? What
are the repercussions of using comments in this fashion?</P>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=189789"></A>10.73 (*Deferred
constants, 15 min.) "If the assignment symbol <CODE>':='</CODE> followed
by an expression is not present in a constant declaration, then the declaration
declares a deferred constant. Such a constant declaration may only appear
in a package declaration. The corresponding full constant declaration, which
defines the value of the constant, must appear in the body of the package"
[<A HREF="../../VHDL/LRM/HTML/1076_4.HTM#4.3.1.1">VHDL 93LRM4.3.1.1</A>].</P>
<PRE><B>package</B> Constant <B>is constant</B> s1, s2 : BIT_VECTOR; <B>end</B> Constant;
<B>package body</B> Constant <B>is</B>
<B>constant</B> s0 : BIT_VECTOR := "00"; <B>constant</B> s1 : BIT_VECTOR := "01";
<B>end</B> Constant;</PRE>
<P><P CLASS="Exercise"><A NAME="pgfId=192453"></A>It is tempting to use
deferred constants to hide information. However, there are problems with
this approach. Analyze the following code, explain the results, and correct
the problems:</P>
<PRE><B>entity</B> Deferred_1 <B>is</B> <B>end</B>; <B>architecture</B> Behave <B>of</B> Deferred_1 <B>is</B>
<B>use </B>work.<B>all</B>; <B>signal </B>y,i1,i2 : INTEGER; <B>signal</B> sel : INTEGER <B>range</B> 0 <B>to</B> 1;
<B>begin with</B> sel <B>select</B> y <= i1 <B>when</B> s0, i2 <B>when</B> s1; <B>end</B>;</PRE>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=372079"></A>10.74 (***Viterbi
code, days) Convert the Verilog model of the Viterbi decoder in Chapter 11
to VHDL. This problem is tedious without the help of some sort of Verilog
to VHDL conversion process. There are two main approaches to this problem.
The first uses a synthesis tool to read the behavioral Verilog and write
structural VHDL (the Compass ASIC Synthesizer can do this, for example).
The second approach uses conversion programs (Alternative System Concepts
Inc. at <CODE>http://www.ascinc.com</CODE> is one source). Some of these
companies allow you to e-mail code to them and they will automatically return
a translated version.</P>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=199750"></A>10.75 (*Wait
statement, 30 min.) Rewrite the code below using a single <CODE>wait</CODE>
statement and write a testbench to prove that both approaches are exactly
equivalent:</P>
<PRE><B>entity</B> Wait_Exit <B>is</B> <B>port</B> (Clk : <B>in</B> BIT); <B>end</B>;
<B>architecture</B> Behave <B>of</B> Wait_Exit <B>is</B>
<B>begin</B> <B>process begin</B>
<B>loop wait</B> <B>on</B> Clk; <B>exit</B> <B>when</B> Clk = '1'; <B>end</B> <B>loop</B>;
<B>end</B> <B>process</B>;
<B>end</B>;</PRE>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=201471"></A>10.76 (Expressions,
10 min.) Explain and correct the problems with the following:</P>
<PRE><B>variable</B> b : BOOLEAN; b := "00" < "11";
<B>variable</B> bv8 : BIT_VECTOR (7 <B>downto</B> 0) := "1000_0000";</PRE>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=222271"></A>10.77 (Combinational
logic using <CODE>case</CODE> statement, 10 min.) A Verilog user suggests
the following method to model combinational logic. What are the problems
with this approach? Can you get it to work?</P>
<PRE><B>entity</B> AndCase <B>is</B> <B>port</B> (a, b : BIT; y : <B>out</B> BIT); <B>end</B>;
<B>architecture</B> Behave <B>of</B> AndCase <B>is begin</B> <B>process</B> (a , b) <B>begin</B>
<B> case</B> a & b <B>is</B>
<B> when</B> '1'&'1' => y <= '1'; <B>when</B> <B>others</B> => y <= '0';
<B> end</B> <B>case</B>;
<B>end</B> <B>process</B>; <B>end</B>;</PRE>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=221667"></A>10.78 (*Generics
and back-annotation, 60 min.)</P>
<P><P CLASS="ExercisePartFirst"><A NAME="pgfId=537673"></A>Construct design
entities And_3(Behave), a two-input AND gate, and <CODE>Xor_3(Behave)</CODE>
, a two-input XOR gate. Include generic constants to model the propagation
delay from each input to the output separately. Use the following entity
declaration for And_3:</P>
<PRE><B>entity</B> And_3 <B>is</B> <B>port</B> (I1, I2 : BIT; O : <B>out</B> BIT);
<B>generic</B> (I1toO, I2toO : DELAY_LENGTH := 0.4 ns); <B>end</B>;</PRE>
<P><P CLASS="ExercisePart"><A NAME="pgfId=466438"></A>Create and test a
package, P_1, that contains And_3 and <CODE>Xor_3</CODE> as components.</P>
<P><P CLASS="ExercisePart"><A NAME="pgfId=466452"></A>Create and test a
design entity Half_Adder_3<CODE> (Structure_3)</CODE> that uses P_1, with
the following interface:</P>
<PRE><B>entity</B> Half_Adder_3 <B>is</B> <B>port</B> (X, Y : BIT; Sum, Carry : <B>out</B> BIT); <B>end</B>;</PRE>
<P><P CLASS="ExercisePart"><A NAME="pgfId=466465"></A>Modify and test the
architecture Structure_3 for Half_Adder_3 so that you can use the following
configuration:</P>
<PRE><B>configuration</B> Structure_3 <B>of</B> Half_Adder_3 <B>is</B>
<B>for</B> Structure_3
<B>for</B> L1 : XOR <B>generic</B> <B>map</B> (0.66 ns,0.69 ns); <B>end</B> <B>for</B>;
<B>for</B> L2 : AND <B>generic</B> <B>map</B> (0.5 ns, 0.6 ns) <B>port</B> <B>map</B> (I2 => HI); <B>end</B> <B>for</B>;
<B>end</B> <B>for</B>; <B>end</B>;</PRE>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=235175"></A>10.79 (SNUG'95,
*60 min.) In 1995 John Cooley organized a contest between VHDL and Verilog
for ASIC designers. The goal was to design the fastest 9-bit counter in
under one hour using Synopsys synthesis tools and an LSI Logic vendor technology
library. The VHDL interface is as follows:</P>
<PRE><B>library</B> ieee; <B>use</B> ieee.std_logic_1164.<B>all</B>;
-- use ieee.std_logic_arith.all; -- substitute your package here
<B>entity</B> counter <B>is port</B> (
data_in : <B>in</B> std_logic_vector(8 <B>downto</B> 0);
up : <B>in</B> std_logic;
down : <B>in</B> std_logic;
clock : <B>in</B> std_logic;
count_out : <B>inout</B> std_logic_vector(8 <B>downto</B> 0);
carry_out : <B>out</B> std_logic;
borrow_out : <B>out</B> std_logic;
parity_out : <B>out</B> std_logic ); <B>end</B> counter;
<B>architecture</B> example <B>of</B> counter <B>is</B> <B>begin</B>
-- insert your design here
<B>end</B> example;</PRE>
<P><P CLASS="Exercise"><A NAME="pgfId=342661"></A>The counter is positive-edge
triggered, counts up with <CODE>up = '1'</CODE> and down with <CODE>down
= '1'</CODE> . The contestants had the advantage of a predefined testbench
with a set of test vectors, you do not. Design a model for the counter and
a testbench. How confident are you that you have thoroughly tested your
model? (In the real contest none of the VHDL contestants managed to even
complete a working design in under one hour. In addition, the VHDL experts
that had designed the testbench omitted a test case for one of the design
specifications.)</P>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=239339"></A>10.80 (*A test
procedure, 45 min.) Write a procedure <CODE>all</CODE> (for a package <CODE>test</CODE>
) that serially generates all possible input values for a signal spaced
in time by a delay, <CODE>dly</CODE> . Use the following interface:</P>
<PRE><B>library</B> ieee; <B>use</B> ieee.std_logic_1164.<B>all</B>; <B>package</B> test <B>is</B>
<B>procedure</B> all (<B>signal</B> SLV : <B>out</B> STD_LOGIC_VECTOR; dly : <B>in</B> TIME);
<B>end</B> <B>package</B> test ;</PRE>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=239732"></A>10.81 (Direct
instantiation, 20 min.) Write an architecture for a full-adder, entity Full_Adder_2,
that directly instantiates units And_2(Behave) and Xor_2(Behave). This is
only possible in a VHDL-93 environment.</P>
<PRE><B>entity</B> And_2 <B>is</B> <B>port</B> (i1, i2 : BIT; y : <B>out</B> BIT); <B>end</B>;
<B>entity</B> Xor_2 <B>is</B> <B>port</B> (i1, i2 : BIT; y : <B>out</B> BIT); <B>end</B>;
<B>entity</B> Full_Adder_2 <B>is</B> <B>port</B> (a, b, c : BIT ; sum, cout : <B>out</B> BIT); <B>end</B>;</PRE>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=372441"></A>10.82 (**Shift
operators for 1164, 60 min.) Write a package body to implement the VHDL-93
shift operators, sll and srl, for the type STD_LOGIC_VECTOR. Use the following
package header:</P>
<PRE><B>package</B> 1164_shift <B>is</B>
<B>function </B>"sll"(x : STD_LOGIC_VECTOR; n : INTEGER)
<B>return </B>STD_LOGIC_VECTOR;
<B>function </B>"srl"(x : STD_LOGIC_VECTOR; n : INTEGER)
<B>return </B>STD_LOGIC_VECTOR;
<B>end</B> <B>package</B> 1164_shift;</PRE>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=366759"></A>10.83 (**VHDL
<CODE>wait</CODE> statement, 60 min.) What is the problem with the following
VHDL code? <EM>Hint:</EM> You may need to consult the VHDL LRM.</P>
<PRE><B>procedure</B> p <B>is begin wait</B> <B>on</B> b; <B>end</B>;
<B>process</B> (a) <B>is begin procedure</B> p; <B>end</B> <B>process</B>;</PRE>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=405713"></A>10.84 (**Null
range, 45 min.) A range such as <CODE>1 to -1</CODE> or <CODE>0 downto 1</CODE>
is a null range (<CODE> 0 to 0</CODE> is a legal range). Write
a one-page summary on null ranges, including code examples. Is a null range
treated as an ascending or descending range?</P>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=405735"></A>10.85 (**Loops,
45 min.) Investigate the following issues with loops, including code examples
and the results of analysis and simulation:</P>
<P><P CLASS="ExercisePartFirst"><A NAME="pgfId=405772"></A>Try to alter
the loop parameter within a loop. What happens?</P>
<P><P CLASS="ExercisePart"><A NAME="pgfId=405773"></A>What is the type of
the loop parameter?</P>
<P><P CLASS="ExercisePart"><A NAME="pgfId=405785"></A>Can the condition
inside a loop depend on a loop parameter?</P>
<P><P CLASS="ExercisePart"><A NAME="pgfId=405774"></A>What happens in a
<CODE>for</CODE> loop if the range is null?</P>
<P><P CLASS="ExercisePart"><A NAME="pgfId=405775"></A>Can you pass a loop
parameter out of a procedure as a procedure parameter?</P>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=425684"></A>10.86 (Signals
and variables, 30 min.) Write a summary on signals and variables, including
code examples.</P>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=425712"></A>10.87 (Type conversion,
60 min.) There are some very subtle rules involving type conversion, [<A HREF="../../VHDL/LRM/HTML/1076_7.HTM#7.3.5">VHDL 93LRM7.3.5]</A>. Does the following
work? Explain the type conversion rules.</P>
<PRE>BV <= BIT_VECTOR("1111");</PRE>
<P><HR ALIGN="LEFT"></P>
<P><A HREF="CH10.htm">Chapter start</A> <A HREF="CH10.17.htm">Previous page</A> <A HREF="CH10.19.htm">Next page</A>
</BODY>
<!--#include file="Copyright.html"--><!--#include file="footer.html"-->
⌨️ 快捷键说明
复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?