ch10.18.htm
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<P><P CLASS="Exercise"><A NAME="pgfId=10450"></A>An interesting class project
is to collect statistics from other students working on this problem and
create a table showing the types and frequency of syntax errors made with
each compile step, and the number of compile steps required. Does this information
suggest ways that you could improve the compiler, or suggest a new type
of tool to use when writing VHDL?</P>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=11334"></A>10.42 (Port maps,
5 min.) What is wrong with this VHDL statement?</P>
<PRE>U1 : nand2 <B>port</B> <B>map</B> (a <= set, b <= qb, c <= q);</PRE>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=358586"></A>10.43 (DRIVING_VALUE,
15 min.) Use the VHDL-93 attribute Clock'DRIVING_VALUE to rewrite the following
clock generator model without using a temporary variable.</P>
<PRE><B>entity</B> ClockGen_2 <B>is</B> <B>port</B> (Clock : <B>out</B> BIT); <B>end</B>;
<B>architecture</B> Behave <B>of</B> ClockGen_2 <B>is</B>
<B>begin process</B> <B>variable</B> Temp : BIT := '1'; <B>begin</B>
Temp := <B>not</B> Temp ; Clock <= Temp <B>after</B> 10 ns; <B>wait</B> <B>for</B> 10 ns;
<B>if</B> (now > 100 ns) <B>then</B> <B>wait</B>; <B>end</B> <B>if</B>; <B>end</B> <B>process</B>;
<B>end</B>;</PRE>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=99747"></A>10.44 (Records,
15 min.) Write an architecture (based on the following skeleton) that uses
the record structure shown:</P>
<PRE><B>entity</B> Test_Record_1 <B>is</B> <B>end</B>; <B>architecture</B> Behave <B>of</B> Test_Record_1 <B>is</B>
<B>begin</B> <B>process</B> <B>type</B> Coordinate <B>is</B> <B>record</B> X, Y : INTEGER; <B>end</B> <B>record</B>;
-- a record declaration for an attribute declaration:
<B>attribute</B> Location:Coordinate; -- an attribute declaration
<B>begin</B> <B>wait</B>; <B>end</B> <B>process</B>; <B>end </B>Behave;</PRE>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=11641"></A>10.45 (**Communication
between processes, 30 min.) Explain and correct the problem with the following
skeleton code:</P>
<PRE><B>variable</B> v1 : INTEGER := 1; <B>process</B> <B>begin </B>v1 := v1+3; <B>wait</B>; <B>end</B> <B>process</B>;
<B>process variable</B> v2 : INTEGER := 2; <B>begin </B>v2 := v1 ; <B>wait</B>; <B>end</B> <B>process</B>;</PRE>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=11661"></A>10.46 (*Resolution,
30 min.) Explain and correct the problems with the following:</P>
<PRE><B>entity</B> R_Bad_1 <B>is port</B> (i : <B>in</B> BIT; o <B>out</B> BIT); <B>end</B>;
<B>architecture</B> Behave <B>of</B> R_Bad_1 <B>is</B>
<B>begin </B>o <= <B>not</B> i <B>after</B> 1 ns; o <= i <B>after</B> 2 ns; <B>end</B>;</PRE>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=361559"></A>10.47 (*Inputs,
30 min.) Analyze the following and explain the result:</P>
<PRE><B>entity</B> And2 <B>is</B> <B>port</B> (A1, A2: <B>in</B> BIT; ZN: <B>out</B> BIT); <B>end</B>;
<B>architecture</B> Simple <B>of</B> And2 <B>is begin</B> ZN <= A1 <B>and</B> A2; <B>end</B>;
<B>entity</B> Input_Bad_1 <B>is end</B>; <B>architecture</B> Netlist <B>of</B> Input_Bad_1 <B>is</B>
<B>component</B> And2 <B>port</B> (A1, A2 : <B>in</B> BIT; ZN : <B>out</B> BIT); <B>end</B> <B>component</B>;
<B>signal</B> X, Z : BIT<B> begin</B> G1 : And2 <B>port</B> <B>map</B> (X, X, Z); <B>end</B>;</PRE>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=13434"></A>10.48 (Association,
15 min.) Analyze the following and explain the problem:</P>
<PRE><B>entity</B> And2 <B>is</B> <B>port</B> (A1, A2 : <B>in</B> BIT; ZN : <B>out</B> BIT); <B>end</B>;
<B>architecture</B> Simple <B>of</B> And2 <B>is begin</B> ZN <= A1 <B>and</B> A2; <B>end</B>;
<B>entity</B> Assoc_Bad_1 <B>is port</B> (<B>signal</B> X, Y : <B>in</B> BIT; Z : <B>out</B> BIT); <B>end</B>;
<B>architecture</B> Netlist <B>of</B> Assoc_Bad_1 <B>is</B>
<B>component</B> And2 <B>port</B> (A1, A2 : <B>in</B> BIT; ZN : <B>out</B> BIT); <B>end</B> <B>component</B>;
<B>begin</B>
G1: And2 <B>port</B> <B>map</B> (X, Y, Z);
G2: And2 <B>port</B> <B>map</B> (A2 => Y, ZN => Z, A1 => X);
G3: And2 <B>port</B> <B>map</B> (X, ZN => Z, A2 => Y);
<B>end</B>;</PRE>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=359933"></A>10.49 (Modes,
30 min.) Analyze and explain the errors in the following:</P>
<PRE><B>entity</B> And2 <B>is</B> <B>port</B> (A1, A2 : <B>in</B> BIT; ZN : <B>out</B> BIT); <B>end</B>;
<B>architecture</B> Simple <B>of</B> And2 <B>is begin</B> ZN <= A1 <B>and</B> A2; <B>end</B>;
<B>entity</B> Mode_Bad_1 <B>is port</B> (X : <B>in</B> BIT; Y : <B>out </B>BIT; Z : <B>inout </B>BIT); <B>end</B>;
<B>architecture</B> Netlist <B>of</B> Mode_Bad_1 <B>is</B>
<B>component</B> And2 <B>port</B> (A1, A2 : <B>in</B> BIT; ZN : <B>out</B> BIT); <B>end</B> <B>component</B>;
<B>begin </B>G1 : And2 <B>port</B> <B>map</B> (X, Y, Z); <B>end</B>;
<B>entity</B> Mode_Bad_2 <B>is port</B> (X : <B>in</B> BIT; Y : <B>out </B>BIT; Z : <B>inout </B>BIT); <B>end</B>;
<B>architecture</B> Netlist <B>of</B> Mode_Bad_1 <B>is</B>
<B>component</B> And2 <B>port</B> (A1, A2 : <B>in</B> BIT; ZN : <B>inout</B> BIT); <B>end</B> <B>component</B>;
<B>begin </B>G1 : And2 <B>port</B> <B>map</B> (X, Y, Z); <B>end</B>;</PRE>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=359968"></A>10.50 (*Mode
association, 60 min.) Analyze and explain the errors in the following code.
The number of errors, types of error, and the information in the error messages
given by different simulators vary tremendously in this area.</P>
<PRE><B>entity</B> Allmode <B>is</B> <B>port</B>
(I : <B>in</B> BIT; O : <B>out</B> BIT; IO : <B>inout</B> BIT; B : <B>buffer</B> BIT);
<B>end</B>;
<B>architecture</B> Simple <B>of</B> Allmode <B>is begin </B>O<=I; IO<=I; B<=I; <B>end</B>;
<B>entity</B> Mode_1 <B>is port</B>
(I : <B>in</B> BIT; O : <B>out</B> BIT; IO : <B>inout</B> BIT; B : <B>buffer</B> BIT);
<B>end</B>;
<B>architecture</B> Netlist <B>of</B> Mode_1 <B>is</B>
<B>component</B> Allmode <B>port</B>
(I : <B>in</B> BIT; O : <B>out</B> BIT; IO : <B>inout</B> BIT; B : <B>buffer</B> BIT); <B>end</B> <B>component</B>;
<B>begin </B>
G1:Allmode <B>port</B> <B>map</B> (I , O , IO, B );
G2:Allmode <B>port</B> <B>map</B> (O , IO, B , I );
G3:Allmode <B>port</B> <B>map</B> (IO, B , I , O );
G4:Allmode <B>port</B> <B>map</B> (B , I , O , IO);
<B>end</B>;</PRE>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=18039"></A>10.51 (**Declarations,
60 min.) Write a tutorial (approximately two pages of text, five pages with
code) with examples explaining the difference between: a component declaration,
a component configuration, a configuration declaration, a configuration
specification, and a block configuration.</P>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=18041"></A>10.52 (**Guards
and guarded signals, 60 min.) Write some simple models to illustrate the
use of guards, guarded signals, and the disconnect statement. Include an
experiment that shows and explains the use of the implicit signal <CODE>GUARD</CODE>
in assignment statements.</P>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=20885"></A>10.53 (**<CODE>
Std_logic_1164</CODE> , 120 min.) Write a short (two pages of text) tutorial,
with (tested) code examples, explaining the <CODE>std_logic_1164 </CODE>types,
their default values, the difference between the <CODE>'ulogic'</CODE> and
<CODE>'logic'</CODE> types, and their vector forms. Include an example that
shows and explains the problem of connecting a <CODE>std_logic_vector</CODE>
to a <CODE>std_ulogic_vector.</CODE></P>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=73456"></A>10.54 (Data swap,
20 min.) Consider the following code:</P>
<PRE><B>library </B>ieee; <B>use </B>ieee.std_logic_1164.<B>all</B>;
<B>package </B>config <B>is</B>
<B>type </B>type1 <B>is record</B>
f1 : std_logic_vector(31 <B>downto</B> 0); f2 : std_logic_vector(3 <B>downto</B> 0);
<B>end record</B>;
<B>type </B>type2 <B>is record</B>
f1 : std_logic_vector(31 <B>downto</B> 0); f2 : std_logic_vector(3 <B>downto</B> 0);
<B>end record</B>;
<B>end </B>config;
<B>library</B> ieee; <B>use</B> ieee.STD_LOGIC_1164.<B>all</B>; <B>use</B> work.config.<B>all</B>;
<B>entity</B> Swap_1 <B>is</B>
<B>port</B> (Data1 : type1; Data2 : type2; sel : STD_LOGIC;
Data1Swap : <B>out</B> type1; Data2Swap : <B>out</B> type2); <B>end</B> Swap_1;
<B>architecture</B> Behave <B>of</B> Swap_1 <B>is</B> <B>begin</B>
Swap: <B>process</B> (Data1, Data2, sel) <B>begin</B> <B>case</B> sel <B>is</B>
<B>when</B> '0' => Data1Swap <= Data1; Data2Swap <= Data2;
<B>when</B> <B>others</B> => Data1Swap <= Data2; Data2Swap <= Data1;
<B>end</B> <B>case</B>; <B>end</B> <B>process</B> Swap; <B>end</B> Behave;</PRE>
<P><P CLASS="Exercise"><A NAME="pgfId=368317"></A>Compile this code. What
is the problem? Suggest a fix. Now write a testbench and test your code.
Have you considered all possibilities?</P>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=73776"></A>10.55 (***RTL,
30 min.) "RTL stands for register-transfer level. ...when referencing
VHDL, the term means that the description includes only concurrent signal
assignment statements and possibly block statements. In particular, VHDL
data flow descriptions explicitly do not contain either process statements
(which describe behavior) or component instantiation statements (which describe
structure)" (Dr. VHDL from VHDL International).</P>
<P><P CLASS="ExercisePartFirst"><A NAME="pgfId=192794"></A>With your knowledge
of process statements and components, comment on Dr. VHDL's explanation.</P>
<P><P CLASS="ExercisePart"><A NAME="pgfId=192795"></A>In less than 100 words
offer your own definition of the difference between RTL, data flow, behavioral,
and structural models.</P>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=73774"></A>10.56 (*Operators
<CODE>mod</CODE> and <CODE>rem</CODE> , 20 min.) Confirm and explain the
following:</P>
<PRE> i1 := (-12) <B>rem</B> 7; -- i1 = -5
i2 := 12 <B>rem</B> (-7); -- i2 = 5
i3 := (12) <B>rem</B> (-7); -- i3 = -5
i4 := 12 <B>mod</B> 7; -- i4 = 5
i5 := (-12) <B>mod</B> 7; -- i5 = 2
i6 := 12 <B>mod</B> (-7); -- i6 = -2
i7 := (12) <B>mod</B> (-7); -- i7 = -5</PRE>
<P><P CLASS="Exercise"><A NAME="pgfId=341893"></A>Evaluate <CODE>-5 rem
2</CODE> and explain the result.</P>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=20890"></A>10.57 (***Event
and stable, 60 min.) Investigate the differences between <CODE>clk'EVENT</CODE>
and <CODE>clk'STABLE</CODE> . Write a minitutorial (in the form of a "cheat
sheet") with examples showing the differences and potential dangers
of using <CODE>clk'STABLE</CODE> .</P>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=342643"></A>10.58 (PREP benchmark
#2, 60 min.) The following code models a benchmark circuit used by PREP
to measure the capacity of FPGAs. Rewrite the concurrent signal assignment
statements (labeled mux and comparator) as equivalent processes. Draw a
datapath schematic corresponding to PREP2(Behave_1). Write a testbench for
the model. Finally (for extra credit) rewrite the model and testbench to
use <CODE>STD_LOGIC</CODE> instead of <CODE>BIT</CODE> types.</P>
<PRE><B>library</B> ieee; <B>use</B> ieee.STD_LOGIC_1164.<B>all</B>;
<B>use</B> ieee.NUMERIC_BIT.<B>all</B>; <B>use</B> ieee.NUMERIC_STD.<B>all</B>;
<B>entity</B> PREP2 <B>is</B>
<B>port</B>(CLK,Reset,Sel,Ldli,Ldhi : BIT; D1,D2 : STD_LOGIC_VECTOR(7 <B>downto</B> 0);
DQ:<B>out</B> STD_LOGIC_VECTOR(7 <B>downto</B> 0));
<B>end</B>;
<B>architecture</B> Behave_1 <B>of</B> PREP2 <B>is</B>
<B>signal</B> EQ : BIT; <B>signal</B> y,lo,hi,Q_i : STD_LOGIC_VECTOR(7 <B>downto</B> 0);
<B>begin </B>
outputDriver: Q <= Q_i;
mux: <B>with</B> Sel <B>select</B> y <= hi <B>when</B> '0', D1 <B>when</B> '1';
comparator: EQ <= '1' <B>when</B> Q_i = lo <B>else</B> '0';
register: <B>process</B>(Reset, CLK) <B>begin</B>
<B>if</B> Reset = '1' <B>then</B> hi <= "00000000"; lo <= "00000000";
<B>elsif</B> CLK = '1' <B>and</B> CLK'EVENT <B>then</B>
<B>if</B> Ldhi='1' <B>then</B> hi<=D2;<B>end</B> <B>if</B>;<B>if</B> Ldlo='1' <B>then</B> lo<=D2;<B>end</B> <B>if</B>;
<B>end</B> <B>if</B>;
<B> end</B> <B>process</B> register;
counter: <B>process</B>(Reset, CLK) <B>begin</B>
<B>if</B> Reset = '1' <B>then</B> Q_i <= "00000000";
<B>elsif</B> CLK = '1' <B>and</B> CLK'EVENT <B>then</B>
<B>if</B> EQ = '1' <B>then</B> Q_i <= y;
<B>elsif</B> EQ = '0' <B>then</B> Q_i <= Q_i + "00000001";
<B>end</B> <B>if</B>;
<B>end</B> <B>if</B>;
<B> end</B> <B>process</B> counter;
<B>end</B>;</PRE>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=342583"></A>10.59 (PREP #3,
state machine) Draw the state diagram for the following PREP benchmark (see
Problem 10.58). Is this a Mealy or Moore machine? Write a testbench and
test this code.</P>
<PRE><B>library</B> ieee; <B>use</B> ieee.STD_LOGIC_1164.<B>all</B>;
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