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<H2>10.18 Problems</H2>
<P><P CLASS="Exercise"><A NAME="pgfId=2207"></A>* = Difficult ** = Very
difficult *** = Extremely difficult</P>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=282310"></A>10.1 (Hello World,
10 min.) Set up a new, empty, directory (use <CODE>mkdir VHDL</CODE>
,<CODE> </CODE>for example) to run your VHDL simulator (the exact details
will depend on your computer and simulator). Copy the code below to a file
called<CODE> hw_1.vhd</CODE> in your<CODE> VHDL </CODE>directory (leave
out comments to save typing). Hint: Use the<CODE> vi </CODE>editor (<CODE>
i</CODE> inserts text,<CODE> x</CODE> deletes text, <CODE>dd</CODE> deletes
a line,<CODE> ESC :w</CODE> writes the file, <CODE>ESC :q</CODE>
quits) or use <CODE>cat > hw_1.vhd</CODE> and type in the code
(use <CODE>CTRL-D</CODE> to end typing) on a UNIX machine. Remember to save
in 'Text Only' mode (Frame or MS Word) on an IBM PC or Apple Macintosh.</P>
<P><P CLASS="Exercise"><A NAME="pgfId=282359"></A>Analyze, elaborate, and
simulate your model (include the output in your answer). Comment on how
easy or hard it was to follow the instructions to use the software and suggest
improvements.</P>
<PRE><B>entity</B> HW_1 <B>is</B> <B>end</B>; <B>architecture</B> Behave <B>of</B> HW_1 <B>is</B>
<B>constant</B> M : STRING := "hello, world"; <B>signal</B> Ch : CHARACTER := ' ';
<B>begin</B> <B>process</B> <B>begin</B>
<B>for</B> i <B>in</B> M'RANGE <B>loop</B> Ch <= M(i); <B>wait</B> <B>for</B> 1 ns; <B>end</B> <B>loop</B>; <B>wait</B>;
<B>end</B> <B>process</B>; <B>end</B>;</PRE>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=282348"></A>10.2 (Running
a VHDL simulation, 20 min.) Copy the example from Section 10.1 into
a file called <CODE>Counter1.vhd</CODE> in your<CODE> VHDL </CODE>directory
(leave out the comments to save typing). Complete the compile (analyze),
elaborate (build), and execute (initialize and simulate) or other equivalent
steps for your simulator. After each step list the contents of your directory
<CODE>VHDL </CODE>and any subdirectories and files that are created (use
<CODE>ls -alR</CODE> on a UNIX system).</P>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=284207"></A>10.3 (Simulator
commands, 10 min.) Make a "cheat sheet" for your simulator, listing
the commands that can be used to control simulation.</P>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=133507"></A>10.4 (BNF addresses,
10 min.) Create a BNF description of a name including: optional title (Prof.,
Dr., Mrs., Mr., Miss, or Ms.), optional first name and middle initials (allow
up to two), and last name (including unusual hyphenated and foreign names,
such as Miss A-S. de La Salle, and Prof. John T. P. McTavish-f Fiennes).
The lowest level constructs are <CODE>letter ::= a-Z</CODE> ,
<CODE>'.'</CODE> (period) and <CODE>'-'</CODE> (hyphen). Add BNF productions
for a postal address in the form: company name, mail stop, street address,
address lines (1 to 4), and country.</P>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=254727"></A>10.5 (BNF e-mail,
10 min.) Create a BNF description of a valid internet e-mail address in
terms of letters, <CODE>'@'</CODE> , <CODE>'.'</CODE> , <CODE>'gov'</CODE>
, <CODE>'com</CODE> ', <CODE>'org</CODE> ', and <CODE>'edu'</CODE> . Create
a state diagram that "parses" an e-mail address for validity.</P>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=359424"></A>10.6 (BNF equivalence)
Are the following BNF productions exactly equivalent? If they are not, produce
a counterexample that shows a difference.</P>
<PRE> term ::= factor { multiplying_operator factor }
term ::= factor | term multiplying_operator factor</PRE>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=145803"></A>10.7 (Environment,
20 min.) Write a simple VHDL model to check and demonstrate that you can
get to the IEEE library and have the environment variables, library statements,
and such correctly set up for your simulator.</P>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=145807"></A>10.8 (Work, 20
min.) Write simple VHDL models to demonstrate that you can retrieve and
use previously analyzed design units from the library<CODE> work </CODE>and
that you can also remove design units from<CODE> work</CODE> . Explain how
your models prove that access to<CODE> work</CODE> is functioning correctly.</P>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=145817"></A>10.9 (Packages,
60 min.) Write a simple package (use filename <CODE>PackH.vhd</CODE> ) and
package body (filename <CODE>PackB.vhd</CODE> ). Demonstrate that you can
store your package (call it<CODE> MyPackage</CODE> ) in the library <CODE>work</CODE>
. Then store, move, or rename (the details will depend on your software)
your package to a library called <CODE>MyLibrary</CODE> in a directory called
<CODE>MyDir</CODE> , and use its contents with a library clause (<CODE>
library MyLibrary</CODE> ) and a use clause (<CODE> use MyLibrary.MyPackage.all</CODE>
) in a testbench called <CODE>PackTest</CODE> (filename <CODE>PackT.vhd</CODE>
) in another directory <CODE>MyWork</CODE> . You may or may not be amazed
at how complicated this can be and how poorly most software companies document
this process.</P>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=145839"></A>10.10 (***IEEE Std 1164,
60 min.) Prior to VHDL-93 the <CODE>xnor</CODE> function was not available,
and therefore older versions of the <CODE>std_logic_1164</CODE> library
did not provide the <CODE>xnor</CODE> function for <CODE>STD_LOGIC</CODE>
types either (it was actually included but commented out). Write a simple
model that checks to see if you have the newer version of <CODE>std_logic_1164</CODE>
. Can you do this without crashing the simulator?</P>
<P><P CLASS="Exercise"><A NAME="pgfId=145840"></A>You are an engineer on
a very large project and find that your design fails to compile because
your design must use the <CODE>xnor</CODE> function and the library setup
on your company's system still points to the old IEEE <CODE>std_logic_1164</CODE>
library, even though the new library was installed. You are apparently the
first person to realize the problem. Your company has a policy that any
time a library is changed all design units that use that library must be
rebuilt from source. This might require days or weeks of work. Explain in
detail, using code, the alternative solutions. What will you recommend to
your manager?</P>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=201380"></A>10.11 (**VHDL-93
test, 20 min.) Write a simple test to check if your simulator is a VHDL-87
or VHDL-93 environment--without crashing the simulator.</P>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=251747"></A>10.12 (Declarations,
10 min.) Analyze the following changes to the code in Section 10.8
and include the simulator output in your answers:</P>
<P><P CLASS="ExercisePartFirst"><A NAME="pgfId=114962"></A>Uncomment the
declarations for<CODE> Bad100 </CODE>and<CODE> Bad4 </CODE>in Declaration<CODE>
_1</CODE> .</P>
<P><P CLASS="ExercisePart"><A NAME="pgfId=114966"></A>Add the following
to Constant_2:</P>
<PRE><B>signal</B> wacky : wackytype (31 <B>downto</B> 0); -- wacky</PRE>
<P><P CLASS="ExercisePart"><A NAME="pgfId=115049"></A>Remove the library
and use clause in Constant_2.</P>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=424164"></A>10.13 (<CODE>
STRING</CODE> type, 10 min.) Replace the<CODE> write </CODE>statement that
prints the string <CODE>" count="</CODE> in <CODE>Text(Behave)</CODE>
in Section 10.6.3 with the following, compile it, and explain the result:</P>
<PRE>write(L, " count=" ); -- No type qualification.</PRE>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=221568"></A>10.14 (Sequential
statements, 10 min.) Uncomment the following line in Wait_1(Behave) in Section 10.10,
analyze the code, and explain the result:</P>
<PRE><B>wait</B> <B>on</B> x(1 <B>to</B> v); -- v is a variable.</PRE>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=114906"></A>10.15 (VHDL logical
operators, 10 min.)</P>
<P><P CLASS="ExercisePartFirst"><A NAME="pgfId=20726"></A>Explain the problem
with the following VHDL statement:</P>
<PRE>Z <= A <B>nand</B> B <B>nand</B> C;</PRE>
<P><P CLASS="ExercisePart"><A NAME="pgfId=2239"></A>Explain why this problem
does not occur with this statement:</P>
<PRE>Z <= A <B>and</B> B <B>and</B> C;</PRE>
<P><P CLASS="ExercisePart"><A NAME="pgfId=2245"></A>What can you say about
the logical operators: <CODE>and</CODE> , <CODE>or</CODE> , <CODE>nand</CODE>
, <CODE>nor</CODE> , <CODE>xnor</CODE> , <CODE>xor</CODE> ?</P>
<P><P CLASS="ExercisePart"><A NAME="pgfId=20732"></A>Is the following code
legal?</P>
<PRE>Z <= A <B>and</B> B <B>or </B>C;</PRE>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=372605"></A>10.16 (*Initialization,
45 min.) Consider the following code:</P>
<PRE><B>entity</B> DFF_Plain <B>is</B> port (Clk, D : <B>in</B> BIT; Q : <B>out</B> BIT); <B>end</B>;
<B>architecture</B> Bad <B>of</B> DFF_Plain <B>is begin process</B> (Clk) <B>begin</B>
<B>if</B> Clk = '0' <B>and</B> Clk'EVENT <B>then </B>Q <= D <B>after</B> 1 ns; <B>end</B> <B>if</B>;
<B>end</B> <B>process</B>; <B>end</B>;</PRE>
<P><P CLASS="ExercisePartFirst"><A NAME="pgfId=5306"></A>Analyze and simulate
this model using a testbench.</P>
<P><P CLASS="ExercisePart"><A NAME="pgfId=153455"></A>Rewrite architecture
<CODE>Bad</CODE> using an equivalent <CODE>process</CODE> including a <CODE>wait</CODE>
statement. Simulate this equivalent model and confirm the behaviors are
identical.</P>
<P><P CLASS="ExercisePart"><A NAME="pgfId=20723"></A>What is the behavior
of the output <CODE>Q</CODE> during initial execution of the process?</P>
<P><P CLASS="ExercisePart"><A NAME="pgfId=20724"></A>Why does this happen?</P>
<P><P CLASS="ExercisePart"><A NAME="pgfId=20725"></A>Why does this not happen
with the following code:</P>
<PRE><B>architecture</B> Good <B>of</B> DFF_Plain <B>is</B>
<B>begin process begin wait</B> <B>until</B> Clk = '0'; Q <= D <B>after</B> 1 ns;
<B>end</B> <B>process</B>; <B>end</B>;</PRE>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=5320"></A>10.17 (Initial
and default values, 20 min.) Use code examples to explain the difference
between: default expression, default value, implicit default value, initial
value, initial value expression, and default initial value.</P>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=361438"></A>10.18 (Enumeration
types, 20 min.) Explain the analysis results for the following:</P>
<PRE><B>type</B> MVL4 <B>is</B> ('X', '0', '1', 'Z'); <B>signal</B> test : MVL4;
<B>process begin</B>
test <= 1; test <= Z; test <= z; test <= '1'; test <= 'Z';
<B>end</B> <B>process</B>;</PRE>
<P><P CLASS="Exercise"><A NAME="pgfId=7264"></A>Alter the type declaration
to the following, analyze your code again, and comment:</P>
<PRE><B>type</B> Mixed4 <B>is</B> (X , '0', '1', Z);</PRE>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=88499"></A>10.19 (Type declarations,
10 min.) Correct these declarations:</P>
<PRE><B>type</B> BadArray <B>is</B> <B>array</B> (0 <B>to</B> 7) <B>of</B> BIT_VECTOR;
<B>type</B> Byte <B>is</B> <B>array</B> (NATURAL <B>range</B> 7 <B>downto</B> 0) <B>of</B> BIT;
<B>subtype</B> BadNibble <B>is</B> Byte(3 <B>downto</B> 0);
<B>type</B> BadByte <B>is</B> <B>array</B> (<B>range</B> 7 <B>downto</B> 0) <B>of</B> BIT;</PRE>
<P><P CLASS="ExerciseHead"><A NAME="pgfId=254168"></A>10.20 (Procedure
parameters, 10 min.) Analyze the following package; explain and correct
the error. Finally, build a testbench to check your solution.</P>
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