float_add_modue_map.mrp

32位单精度浮点加法器

Release 14.2 Map P.28xd (nt64)
Xilinx Mapping Report File for Design 'float_add_modue'

Design Information
------------------
Command Line   : map -intstyle ise -p xc7vx485t-ffg1761-2 -w -logic_opt off -ol
high -t 1 -xt 0 -register_duplication off -r 4 -mt off -ir off -pr off -lc off
-power off -o float_add_modue_map.ncd float_add_modue.ngd float_add_modue.pcf 
Target Device  : xc7vx485t
Target Package : ffg1761
Target Speed   : -2
Mapper Version : virtex7 -- $Revision: 1.55 $
Mapped Date    : Sat Dec 22 22:59:58 2012

Design Summary
--------------
Number of errors:      0
Number of warnings:  376
Slice Logic Utilization:
  Number of Slice Registers:                   331 out of 607,200    1%
    Number used as Flip Flops:                 331
    Number used as Latches:                      0
    Number used as Latch-thrus:                  0
    Number used as AND/OR logics:                0
  Number of Slice LUTs:                      1,151 out of 303,600    1%
    Number used as logic:                    1,149 out of 303,600    1%
      Number using O6 output only:             839
      Number using O5 output only:              23
      Number using O5 and O6:                  287
      Number used as ROM:                        0
    Number used as Memory:                       0 out of 130,800    0%
    Number used exclusively as route-thrus:      2
      Number with same-slice register load:      0
      Number with same-slice carry load:         2
      Number with other load:                    0

Slice Logic Distribution:
  Number of occupied Slices:                   449 out of  75,900    1%
  Number of LUT Flip Flop pairs used:        1,161
    Number with an unused Flip Flop:           886 out of   1,161   76%
    Number with an unused LUT:                  10 out of   1,161    1%
    Number of fully used LUT-FF pairs:         265 out of   1,161   22%
    Number of unique control sets:              12
    Number of slice register sites lost
      to control set restrictions:              53 out of 607,200    1%

  A LUT Flip Flop pair for this architecture represents one LUT paired with
  one Flip Flop within a slice.  A control set is a unique combination of
  clock, reset, set, and enable signals for a registered element.
  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.
  OVERMAPPING of BRAM resources should be ignored if the design is
  over-mapped for a non-BRAM resource or if placement fails.

IO Utilization:
  Number of bonded IOBs:                       374 out of     700   53%

Specific Feature Utilization:
  Number of RAMB36E1/FIFO36E1s:                  0 out of   1,030    0%
  Number of RAMB18E1/FIFO18E1s:                  0 out of   2,060    0%
  Number of BUFG/BUFGCTRLs:                      1 out of      32    3%
    Number used as BUFGs:                        1
    Number used as BUFGCTRLs:                    0
  Number of IDELAYE2/IDELAYE2_FINEDELAYs:        0 out of     700    0%
  Number of ILOGICE2/ILOGICE3/ISERDESE2s:        0 out of     700    0%
  Number of ODELAYE2/ODELAYE2_FINEDELAYs:        0 out of     700    0%
  Number of OLOGICE2/OLOGICE3/OSERDESE2s:        0 out of     700    0%
  Number of PHASER_IN/PHASER_IN_PHYs:            0 out of      56    0%
  Number of PHASER_OUT/PHASER_OUT_PHYs:          0 out of      56    0%
  Number of BSCANs:                              0 out of       4    0%
  Number of BUFHCEs:                             0 out of     168    0%
  Number of BUFRs:                               0 out of      56    0%
  Number of CAPTUREs:                            0 out of       1    0%
  Number of DNA_PORTs:                           0 out of       1    0%
  Number of DSP48E1s:                            0 out of   2,800    0%
  Number of EFUSE_USRs:                          0 out of       1    0%
  Number of FRAME_ECCs:                          0 out of       1    0%
  Number of GTXE2_CHANNELs:                      0 out of      56    0%
  Number of GTXE2_COMMONs:                       0 out of      14    0%
  Number of ICAPs:                               0 out of       2    0%
  Number of IDELAYCTRLs:                         0 out of      14    0%
  Number of IN_FIFOs:                            0 out of      56    0%
  Number of MMCME2_ADVs:                         0 out of      14    0%
  Number of OUT_FIFOs:                           0 out of      56    0%
  Number of PCIE_2_1s:                           0 out of       4    0%
  Number of PHASER_REFs:                         0 out of      14    0%
  Number of PHY_CONTROLs:                        0 out of      14    0%
  Number of PLLE2_ADVs:                          0 out of      14    0%
  Number of STARTUPs:                            0 out of       1    0%
  Number of XADCs:                               0 out of       1    0%

Average Fanout of Non-Clock Nets:                4.73

Peak Memory Usage:  1485 MB
Total REAL time to MAP completion:  5 mins 22 secs 
Total CPU time to MAP completion:   5 mins 10 secs 

Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Timing Report
Section 11 - Configuration String Information
Section 12 - Control Set Information
Section 13 - Utilization by Hierarchy

Section 1 - Errors
------------------

Section 2 - Warnings
--------------------
WARNING:LIT:701 - PAD symbol "CLK" has an undefined IOSTANDARD.
WARNING:LIT:702 - PAD symbol "CLK" is not constrained (LOC) to a specific
   location.
WARNING:PhysDesignRules:2452 - The IOB SQ_TempB<7> is either not constrained
   (LOC) to a specific location and/or has an undefined I/O Standard
   (IOSTANDARD). This condition may seriously affect the device and will be an
   error in bitstream creation. It should be corrected by properly specifying
   the pin location and I/O Standard.
WARNING:PhysDesignRules:2452 - The IOB SQ_TempB<8> is either not constrained
   (LOC) to a specific location and/or has an undefined I/O Standard
   (IOSTANDARD). This condition may seriously affect the device and will be an
   error in bitstream creation. It should be corrected by properly specifying
   the pin location and I/O Standard.
WARNING:PhysDesignRules:2452 - The IOB SQ_TempB<5> is either not constrained
   (LOC) to a specific location and/or has an undefined I/O Standard
   (IOSTANDARD). This condition may seriously affect the device and will be an
   error in bitstream creation. It should be corrected by properly specifying
   the pin location and I/O Standard.
WARNING:PhysDesignRules:2452 - The IOB SQ_TempB<6> is either not constrained
   (LOC) to a specific location and/or has an undefined I/O Standard
   (IOSTANDARD). This condition may seriously affect the device and will be an
   error in bitstream creation. It should be corrected by properly specifying
   the pin location and I/O Standard.
WARNING:PhysDesignRules:2452 - The IOB SQ_TempB<9> is either not constrained
   (LOC) to a specific location and/or has an undefined I/O Standard
   (IOSTANDARD). This condition may seriously affect the device and will be an
   error in bitstream creation. It should be corrected by properly specifying
   the pin location and I/O Standard.
WARNING:PhysDesignRules:2452 - The IOB SQ_TempB<0> is either not constrained
   (LOC) to a specific location and/or has an undefined I/O Standard
   (IOSTANDARD). This condition may seriously affect the device and will be an
   error in bitstream creation. It should be corrected by properly specifying
   the pin location and I/O Standard.
WARNING:PhysDesignRules:2452 - The IOB SQ_TempB<3> is either not constrained
   (LOC) to a specific location and/or has an undefined I/O Standard
   (IOSTANDARD). This condition may seriously affect the device and will be an
   error in bitstream creation. It should be corrected by properly specifying
   the pin location and I/O Standard.
WARNING:PhysDesignRules:2452 - The IOB SQ_TempB<4> is either not constrained
   (LOC) to a specific location and/or has an undefined I/O Standard
   (IOSTANDARD). This condition may seriously affect the device and will be an
   error in bitstream creation. It should be corrected by properly specifying
   the pin location and I/O Standard.
WARNING:PhysDesignRules:2452 - The IOB SQ_TempB<1> is either not constrained
   (LOC) to a specific location and/or has an undefined I/O Standard
   (IOSTANDARD). This condition may seriously affect the device and will be an
   error in bitstream creation. It should be corrected by properly specifying
   the pin location and I/O Standard.
WARNING:PhysDesignRules:2452 - The IOB SQ_TempB<2> is either not constrained
   (LOC) to a specific location and/or has an undefined I/O Standard
   (IOSTANDARD). This condition may seriously affect the device and will be an
   error in bitstream creation. It should be corrected by properly specifying
   the pin location and I/O Standard.
WARNING:PhysDesignRules:2452 - The IOB Result<17> is either not constrained
   (LOC) to a specific location and/or has an undefined I/O Standard
   (IOSTANDARD). This condition may seriously affect the device and will be an
   error in bitstream creation. It should be corrected by properly specifying
   the pin location and I/O Standard.
WARNING:PhysDesignRules:2452 - The IOB Result<18> is either not constrained
   (LOC) to a specific location and/or has an undefined I/O Standard
   (IOSTANDARD). This condition may seriously affect the device and will be an
   error in bitstream creation. It should be corrected by properly specifying
   the pin location and I/O Standard.
WARNING:PhysDesignRules:2452 - The IOB Result<15> is either not constrained
   (LOC) to a specific location and/or has an undefined I/O Standard
   (IOSTANDARD). This condition may seriously affect the device and will be an
   error in bitstream creation. It should be corrected by properly specifying
   the pin location and I/O Standard.
WARNING:PhysDesignRules:2452 - The IOB Result<16> is either not constrained
   (LOC) to a specific location and/or has an undefined I/O Standard
   (IOSTANDARD). This condition may seriously affect the device and will be an
   error in bitstream creation. It should be corrected by properly specifying
   the pin location and I/O Standard.
WARNING:PhysDesignRules:2452 - The IOB Result<19> is either not constrained
   (LOC) to a specific location and/or has an undefined I/O Standard
   (IOSTANDARD). This condition may seriously affect the device and will be an
   error in bitstream creation. It should be corrected by properly specifying
   the pin location and I/O Standard.
WARNING:PhysDesignRules:2452 - The IOB Result<10> is either not constrained
   (LOC) to a specific location and/or has an undefined I/O Standard
   (IOSTANDARD). This condition may seriously affect the device and will be an