counter8.rpt
来自「xilinx xc9572 cpld 实现的伺服电机控制器」· RPT 代码 · 共 770 行 · 第 1/4 页
RPT
770 行
2 0 0 3 FB2_12 STD 6 I/O (b)
Temp_Maddsub__n0000_Mxor_Result<7>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<7>__n0002<0>_D
2 0 \/1 2 FB2_13 STD 8 I/O (b)
Qout<9> 6 1<- 0 0 FB2_14 STD 9 I/O O
Temp_Maddsub__n0000_Mxor_Result<3>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<3>__n0002<0>_D
2 0 0 3 FB2_15 STD 11 I/O I
Temp_Maddsub__n0000_Mxor_Result<2>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<2>__n0002<0>_D
2 0 0 3 FB2_16 STD 10 I/O (b)
Temp_Maddsub__n0000_Mxor_Result<1>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<1>__n0002<0>_D
2 0 0 3 FB2_17 STD 12 I/O I
Temp_Maddsub__n0000__n0067<0>/Temp_Maddsub__n0000__n0067<0>_D2
3 0 0 2 FB2_18 STD 92 I/O (b)
Signals Used by Logic in Function Block
1: CCLK 11: Qout<2> 20: Temp_Maddsub__n0000_Mxor_Result<8>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<8>__n0002<0>_D
2: CE 12: Qout<3> 21: Temp_Maddsub__n0000_Mxor_Result<9>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<9>__n0002<0>_D
3: CLR 13: Qout<7> 22: Temp_Maddsub__n0000__n0049<0>/Temp_Maddsub__n0000__n0049<0>_D2
4: Din<7> 14: Qout<8> 23: Temp_Maddsub__n0000__n0051<0>/Temp_Maddsub__n0000__n0051<0>_D2
5: Din<8> 15: Qout<9> 24: Temp_Maddsub__n0000__n0059<0>/Temp_Maddsub__n0000__n0059<0>_D2
6: Din<9> 16: Temp_Maddsub__n0000_Mxor_Result<1>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<1>__n0002<0>_D
25: Temp_Maddsub__n0000__n0061<0>/Temp_Maddsub__n0000__n0061<0>_D2
7: L 17: Temp_Maddsub__n0000_Mxor_Result<2>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<2>__n0002<0>_D
26: Temp_Maddsub__n0000__n0063<0>/Temp_Maddsub__n0000__n0063<0>_D2
8: Qout<0> 18: Temp_Maddsub__n0000_Mxor_Result<3>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<3>__n0002<0>_D
27: Temp_Maddsub__n0000__n0065<0>/Temp_Maddsub__n0000__n0065<0>_D2
9: Qout<10> 19: Temp_Maddsub__n0000_Mxor_Result<7>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<7>__n0002<0>_D
28: UP
10: Qout<1>
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
Qout<7> XXXX..X.....X.....X....X................ 8 8
Temp_Maddsub__n0000__n0065<0>/Temp_Maddsub__n0000__n0065<0>_D2
..............X.....X....X.............. 3 3
Temp_Maddsub__n0000__n0063<0>/Temp_Maddsub__n0000__n0063<0>_D2
.............X.....X....X............... 3 3
Temp_Maddsub__n0000__n0061<0>/Temp_Maddsub__n0000__n0061<0>_D2
............X.....X....X................ 3 3
Temp_Maddsub__n0000__n0053<0>/Temp_Maddsub__n0000__n0053<0>_D2
...........X.....X....X................. 3 3
Qout<8> XXX.X.X......X.....X....X............... 8 8
Temp_Maddsub__n0000__n0051<0>/Temp_Maddsub__n0000__n0051<0>_D2
..........X.....X....X.................. 3 3
Temp_Maddsub__n0000__n0049<0>/Temp_Maddsub__n0000__n0049<0>_D2
.......X.......X...........X............ 3 3
Temp_Maddsub__n0000_Mxor_Result<9>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<9>__n0002<0>_D
..............X............X............ 2 2
Temp_Maddsub__n0000_Mxor_Result<8>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<8>__n0002<0>_D
.............X.............X............ 2 2
Temp_Maddsub__n0000_Mxor_Result<7>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<7>__n0002<0>_D
............X..............X............ 2 2
Qout<9> XXX..XX.......X.....X....X.............. 8 8
Temp_Maddsub__n0000_Mxor_Result<3>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<3>__n0002<0>_D
...........X...............X............ 2 2
Temp_Maddsub__n0000_Mxor_Result<2>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<2>__n0002<0>_D
..........X................X............ 2 2
Temp_Maddsub__n0000_Mxor_Result<1>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<1>__n0002<0>_D
.........X.................X............ 2 2
Temp_Maddsub__n0000__n0067<0>/Temp_Maddsub__n0000__n0067<0>_D2
........X.................XX............ 3 3
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 22/14
Number of signals used by logic mapping into function block: 22
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB3_1 41 I/O
(unused) 0 0 \/1 4 FB3_2 32 I/O I
Qout<10> 6 1<- 0 0 FB3_3 STD 49 I/O O
(unused) 0 0 0 5 FB3_4 50 I/O
(unused) 0 0 0 5 FB3_5 35 I/O I
(unused) 0 0 0 5 FB3_6 53 I/O
(unused) 0 0 \/1 4 FB3_7 54 I/O (b)
Qout<2> 6 1<- 0 0 FB3_8 STD 37 I/O O
(unused) 0 0 0 5 FB3_9 42 I/O I
(unused) 0 0 0 5 FB3_10 60 I/O
(unused) 0 0 0 5 FB3_11 52 I/O I
Temp_Maddsub__n0000__n0059<0>/Temp_Maddsub__n0000__n0059<0>_D2
2 0 \/1 2 FB3_12 STD 61 I/O (b)
Qout<4> 6 1<- 0 0 FB3_13 STD 63 I/O O
Temp_Maddsub__n0000__n0057<0>/Temp_Maddsub__n0000__n0057<0>_D2
2 0 0 3 FB3_14 STD 55 I/O (b)
Temp_Maddsub__n0000__n0055<0>/Temp_Maddsub__n0000__n0055<0>_D2
2 0 0 3 FB3_15 STD 56 I/O I
Temp_Maddsub__n0000_Mxor_Result<6>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<6>__n0002<0>_D
2 0 0 3 FB3_16 STD 65 I/O (b)
Temp_Maddsub__n0000_Mxor_Result<5>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<5>__n0002<0>_D
2 0 0 3 FB3_17 STD 58 I/O (b)
Temp_Maddsub__n0000_Mxor_Result<4>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<4>__n0002<0>_D
2 0 0 3 FB3_18 STD 59 I/O (b)
Signals Used by Logic in Function Block
1: CCLK 9: Qout<2> 16: Temp_Maddsub__n0000_Mxor_Result<6>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<6>__n0002<0>_D
2: CE 10: Qout<4> 17: Temp_Maddsub__n0000__n0049<0>/Temp_Maddsub__n0000__n0049<0>_D2
3: CLR 11: Qout<5> 18: Temp_Maddsub__n0000__n0053<0>/Temp_Maddsub__n0000__n0053<0>_D2
4: Din<10> 12: Qout<6> 19: Temp_Maddsub__n0000__n0055<0>/Temp_Maddsub__n0000__n0055<0>_D2
5: Din<2> 13: Temp_Maddsub__n0000_Mxor_Result<2>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<2>__n0002<0>_D
20: Temp_Maddsub__n0000__n0057<0>/Temp_Maddsub__n0000__n0057<0>_D2
6: Din<4> 14: Temp_Maddsub__n0000_Mxor_Result<4>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<4>__n0002<0>_D
21: Temp_Maddsub__n0000__n0065<0>/Temp_Maddsub__n0000__n0065<0>_D2
7: L 15: Temp_Maddsub__n0000_Mxor_Result<5>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<5>__n0002<0>_D
22: UP
8: Qout<10>
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
Qout<10> XXXX..XX............XX.................. 8 8
Qout<2> XXX.X.X.X...X...X....................... 8 8
Temp_Maddsub__n0000__n0059<0>/Temp_Maddsub__n0000__n0059<0>_D2
...........X...X...X.................... 3 3
Qout<4> XXX..XX..X...X...X...................... 8 8
Temp_Maddsub__n0000__n0057<0>/Temp_Maddsub__n0000__n0057<0>_D2
..........X...X...X..................... 3 3
Temp_Maddsub__n0000__n0055<0>/Temp_Maddsub__n0000__n0055<0>_D2
.........X...X...X...................... 3 3
Temp_Maddsub__n0000_Mxor_Result<6>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<6>__n0002<0>_D
...........X.........X.................. 2 2
Temp_Maddsub__n0000_Mxor_Result<5>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<5>__n0002<0>_D
..........X..........X.................. 2 2
Temp_Maddsub__n0000_Mxor_Result<4>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<4>__n0002<0>_D
.........X...........X.................. 2 2
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB4 ***********************************
Number of function block inputs used/remaining: 16/20
Number of signals used by logic mapping into function block: 16
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB4_1 66 I/O
(unused) 0 0 \/1 4 FB4_2 64 I/O I
Qout<3> 6 1<- 0 0 FB4_3 STD 71 I/O O
(unused) 0 0 0 5 FB4_4 72 I/O
(unused) 0 0 0 5 FB4_5 67 I/O I
(unused) 0 0 0 5 FB4_6 76 I/O
(unused) 0 0 \/1 4 FB4_7 77 I/O (b)
Qout<5> 6 1<- 0 0 FB4_8 STD 68 I/O O
(unused) 0 0 0 5 FB4_9 70 I/O
(unused) 0 0 0 5 FB4_10 81 I/O
(unused) 0 0 0 5 FB4_11 74 I/O I
(unused) 0 0 \/1 4 FB4_12 82 I/O (b)
Qout<6> 6 1<- 0 0 FB4_13 STD 85 I/O O
(unused) 0 0 0 5 FB4_14 78 I/O I
(unused) 0 0 0 5 FB4_15 89 I/O I
(unused) 0 0 0 5 FB4_16 86 I/O
(unused) 0 0 0 5 FB4_17 90 I/O I
(unused) 0 0 0 5 FB4_18 79 I/O
Signals Used by Logic in Function Block
1: CCLK 7: L 12: Temp_Maddsub__n0000_Mxor_Result<5>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<5>__n0002<0>_D
2: CE 8: Qout<3> 13: Temp_Maddsub__n0000_Mxor_Result<6>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<6>__n0002<0>_D
3: CLR 9: Qout<5> 14: Temp_Maddsub__n0000__n0051<0>/Temp_Maddsub__n0000__n0051<0>_D2
4: Din<3> 10: Qout<6> 15: Temp_Maddsub__n0000__n0055<0>/Temp_Maddsub__n0000__n0055<0>_D2
5: Din<5> 11: Temp_Maddsub__n0000_Mxor_Result<3>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<3>__n0002<0>_D
16: Temp_Maddsub__n0000__n0057<0>/Temp_Maddsub__n0000__n0057<0>_D2
6: Din<6>
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
Qout<3> XXXX..XX..X..X.......................... 8 8
Qout<5> XXX.X.X.X..X..X......................... 8 8
Qout<6> XXX..XX..X..X..X........................ 8 8
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
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