counter8.rpt

来自「xilinx xc9572 cpld 实现的伺服电机控制器」· RPT 代码 · 共 770 行 · 第 1/4 页

Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.



















FDCPE_Qout0: FDCPE port map (Qout(0),Qout_D(0),CCLK,CLR,'0');
Qout_D(0) <= ((L AND Din(0))
	OR (Qout(0) AND CE AND NOT L)
	OR (NOT Qout(0) AND NOT CE AND NOT L));

FTCPE_Qout10: FTCPE port map (Qout(10),Qout_T(10),CCLK,CLR,'0');
Qout_T(10) <= ((EXP4_.EXP)
	OR (NOT Qout(10) AND L AND Din(10))
	OR (UP AND NOT CE AND NOT L AND 
	Temp_Maddsub__n0000__n0065(0)/Temp_Maddsub__n0000__n0065(0)_D2)
	OR (NOT UP AND NOT CE AND NOT L AND 
	NOT Temp_Maddsub__n0000__n0065(0)/Temp_Maddsub__n0000__n0065(0)_D2));

FTCPE_Qout11: FTCPE port map (Qout(11),Qout_T(11),CCLK,CLR,'0');
Qout_T(11) <= ((EXP0_.EXP)
	OR (NOT Qout(11) AND L AND Din(11))
	OR (UP AND NOT CE AND NOT L AND 
	Temp_Maddsub__n0000__n0067(0)/Temp_Maddsub__n0000__n0067(0)_D2)
	OR (NOT UP AND NOT CE AND NOT L AND 
	NOT Temp_Maddsub__n0000__n0067(0)/Temp_Maddsub__n0000__n0067(0)_D2));

FTCPE_Qout12: FTCPE port map (Qout(12),Qout_T(12),CCLK,CLR,'0');
Qout_T(12) <= ((EXP1_.EXP)
	OR (NOT Qout(12) AND L AND Din(12))
	OR (Qout(11) AND UP AND NOT CE AND NOT L AND 
	Temp_Maddsub__n0000__n0067(0)/Temp_Maddsub__n0000__n0067(0)_D2)
	OR (NOT Qout(11) AND NOT UP AND NOT CE AND NOT L AND 
	NOT Temp_Maddsub__n0000__n0067(0)/Temp_Maddsub__n0000__n0067(0)_D2));

FDCPE_Qout1: FDCPE port map (Qout(1),Qout_D(1),CCLK,CLR,'0');
Qout_D(1) <= ((EXP2_.EXP)
	OR (L AND Din(1))
	OR (Qout(1) AND CE AND NOT L)
	OR (NOT Qout(0) AND NOT CE AND NOT L AND 
	Temp_Maddsub__n0000_Mxor_Result(1)__n0002(0)/Temp_Maddsub__n0000_Mxor_Result(1)__n0002(0)_D));

FDCPE_Qout2: FDCPE port map (Qout(2),Qout_D(2),CCLK,CLR,'0');
Qout_D(2) <= ((EXP5_.EXP)
	OR (L AND Din(2))
	OR (Qout(2) AND CE AND NOT L)
	OR (NOT CE AND NOT L AND 
	NOT Temp_Maddsub__n0000__n0049(0)/Temp_Maddsub__n0000__n0049(0)_D2 AND 
	Temp_Maddsub__n0000_Mxor_Result(2)__n0002(0)/Temp_Maddsub__n0000_Mxor_Result(2)__n0002(0)_D));

FDCPE_Qout3: FDCPE port map (Qout(3),Qout_D(3),CCLK,CLR,'0');
Qout_D(3) <= ((EXP6_.EXP)
	OR (L AND Din(3))
	OR (Qout(3) AND CE AND NOT L)
	OR (NOT CE AND NOT L AND 
	NOT Temp_Maddsub__n0000__n0051(0)/Temp_Maddsub__n0000__n0051(0)_D2 AND 
	Temp_Maddsub__n0000_Mxor_Result(3)__n0002(0)/Temp_Maddsub__n0000_Mxor_Result(3)__n0002(0)_D));

FDCPE_Qout4: FDCPE port map (Qout(4),Qout_D(4),CCLK,CLR,'0');
Qout_D(4) <= ((
	Temp_Maddsub__n0000__n0059(0)/Temp_Maddsub__n0000__n0059(0)_D2.EXP)
	OR (L AND Din(4))
	OR (Qout(4) AND CE AND NOT L)
	OR (NOT CE AND NOT L AND 
	NOT Temp_Maddsub__n0000__n0053(0)/Temp_Maddsub__n0000__n0053(0)_D2 AND 
	Temp_Maddsub__n0000_Mxor_Result(4)__n0002(0)/Temp_Maddsub__n0000_Mxor_Result(4)__n0002(0)_D));

FDCPE_Qout5: FDCPE port map (Qout(5),Qout_D(5),CCLK,CLR,'0');
Qout_D(5) <= ((EXP7_.EXP)
	OR (L AND Din(5))
	OR (Qout(5) AND CE AND NOT L)
	OR (NOT CE AND NOT L AND 
	NOT Temp_Maddsub__n0000__n0055(0)/Temp_Maddsub__n0000__n0055(0)_D2 AND 
	Temp_Maddsub__n0000_Mxor_Result(5)__n0002(0)/Temp_Maddsub__n0000_Mxor_Result(5)__n0002(0)_D));

FDCPE_Qout6: FDCPE port map (Qout(6),Qout_D(6),CCLK,CLR,'0');
Qout_D(6) <= ((EXP8_.EXP)
	OR (L AND Din(6))
	OR (Qout(6) AND CE AND NOT L)
	OR (NOT CE AND NOT L AND 
	NOT Temp_Maddsub__n0000__n0057(0)/Temp_Maddsub__n0000__n0057(0)_D2 AND 
	Temp_Maddsub__n0000_Mxor_Result(6)__n0002(0)/Temp_Maddsub__n0000_Mxor_Result(6)__n0002(0)_D));

FDCPE_Qout7: FDCPE port map (Qout(7),Qout_D(7),CCLK,CLR,'0');
Qout_D(7) <= ((EXP3_.EXP)
	OR (L AND Din(7))
	OR (Qout(7) AND CE AND NOT L)
	OR (NOT CE AND NOT L AND 
	NOT Temp_Maddsub__n0000__n0059(0)/Temp_Maddsub__n0000__n0059(0)_D2 AND 
	Temp_Maddsub__n0000_Mxor_Result(7)__n0002(0)/Temp_Maddsub__n0000_Mxor_Result(7)__n0002(0)_D));

FDCPE_Qout8: FDCPE port map (Qout(8),Qout_D(8),CCLK,CLR,'0');
Qout_D(8) <= ((
	Temp_Maddsub__n0000__n0053(0)/Temp_Maddsub__n0000__n0053(0)_D2.EXP)
	OR (L AND Din(8))
	OR (Qout(8) AND CE AND NOT L)
	OR (NOT CE AND NOT L AND 
	NOT Temp_Maddsub__n0000__n0061(0)/Temp_Maddsub__n0000__n0061(0)_D2 AND 
	Temp_Maddsub__n0000_Mxor_Result(8)__n0002(0)/Temp_Maddsub__n0000_Mxor_Result(8)__n0002(0)_D));

FDCPE_Qout9: FDCPE port map (Qout(9),Qout_D(9),CCLK,CLR,'0');
Qout_D(9) <= ((
	Temp_Maddsub__n0000_Mxor_Result(7)__n0002(0)/Temp_Maddsub__n0000_Mxor_Result(7)__n0002(0)_D.EXP)
	OR (L AND Din(9))
	OR (Qout(9) AND CE AND NOT L)
	OR (NOT CE AND NOT L AND 
	NOT Temp_Maddsub__n0000__n0063(0)/Temp_Maddsub__n0000__n0063(0)_D2 AND 
	Temp_Maddsub__n0000_Mxor_Result(9)__n0002(0)/Temp_Maddsub__n0000_Mxor_Result(9)__n0002(0)_D));


Temp_Maddsub__n0000_Mxor_Result(1)__n0002(0)/Temp_Maddsub__n0000_Mxor_Result(1)__n0002(0)_D <= NOT (UP
	 XOR 
Temp_Maddsub__n0000_Mxor_Result(1)__n0002(0)/Temp_Maddsub__n0000_Mxor_Result(1)__n0002(0)_D <= NOT (Qout(1));


Temp_Maddsub__n0000_Mxor_Result(2)__n0002(0)/Temp_Maddsub__n0000_Mxor_Result(2)__n0002(0)_D <= NOT (UP
	 XOR 
Temp_Maddsub__n0000_Mxor_Result(2)__n0002(0)/Temp_Maddsub__n0000_Mxor_Result(2)__n0002(0)_D <= NOT (Qout(2));


Temp_Maddsub__n0000_Mxor_Result(3)__n0002(0)/Temp_Maddsub__n0000_Mxor_Result(3)__n0002(0)_D <= NOT (UP
	 XOR 
Temp_Maddsub__n0000_Mxor_Result(3)__n0002(0)/Temp_Maddsub__n0000_Mxor_Result(3)__n0002(0)_D <= NOT (Qout(3));


Temp_Maddsub__n0000_Mxor_Result(4)__n0002(0)/Temp_Maddsub__n0000_Mxor_Result(4)__n0002(0)_D <= NOT (UP
	 XOR 
Temp_Maddsub__n0000_Mxor_Result(4)__n0002(0)/Temp_Maddsub__n0000_Mxor_Result(4)__n0002(0)_D <= NOT (Qout(4));


Temp_Maddsub__n0000_Mxor_Result(5)__n0002(0)/Temp_Maddsub__n0000_Mxor_Result(5)__n0002(0)_D <= NOT (UP
	 XOR 
Temp_Maddsub__n0000_Mxor_Result(5)__n0002(0)/Temp_Maddsub__n0000_Mxor_Result(5)__n0002(0)_D <= NOT (Qout(5));


Temp_Maddsub__n0000_Mxor_Result(6)__n0002(0)/Temp_Maddsub__n0000_Mxor_Result(6)__n0002(0)_D <= NOT (UP
	 XOR 
Temp_Maddsub__n0000_Mxor_Result(6)__n0002(0)/Temp_Maddsub__n0000_Mxor_Result(6)__n0002(0)_D <= NOT (Qout(6));


Temp_Maddsub__n0000_Mxor_Result(7)__n0002(0)/Temp_Maddsub__n0000_Mxor_Result(7)__n0002(0)_D <= NOT (UP
	 XOR 
Temp_Maddsub__n0000_Mxor_Result(7)__n0002(0)/Temp_Maddsub__n0000_Mxor_Result(7)__n0002(0)_D <= NOT (Qout(7));


Temp_Maddsub__n0000_Mxor_Result(8)__n0002(0)/Temp_Maddsub__n0000_Mxor_Result(8)__n0002(0)_D <= NOT (UP
	 XOR 
Temp_Maddsub__n0000_Mxor_Result(8)__n0002(0)/Temp_Maddsub__n0000_Mxor_Result(8)__n0002(0)_D <= NOT (Qout(8));


Temp_Maddsub__n0000_Mxor_Result(9)__n0002(0)/Temp_Maddsub__n0000_Mxor_Result(9)__n0002(0)_D <= NOT (UP
	 XOR 
Temp_Maddsub__n0000_Mxor_Result(9)__n0002(0)/Temp_Maddsub__n0000_Mxor_Result(9)__n0002(0)_D <= NOT (Qout(9));


Temp_Maddsub__n0000__n0049(0)/Temp_Maddsub__n0000__n0049(0)_D2 <= ((Qout(0) AND 
	Temp_Maddsub__n0000_Mxor_Result(1)__n0002(0)/Temp_Maddsub__n0000_Mxor_Result(1)__n0002(0)_D)
	OR (NOT UP AND 
	NOT Temp_Maddsub__n0000_Mxor_Result(1)__n0002(0)/Temp_Maddsub__n0000_Mxor_Result(1)__n0002(0)_D));


Temp_Maddsub__n0000__n0051(0)/Temp_Maddsub__n0000__n0051(0)_D2 <= ((Qout(2) AND 
	NOT Temp_Maddsub__n0000_Mxor_Result(2)__n0002(0)/Temp_Maddsub__n0000_Mxor_Result(2)__n0002(0)_D)
	OR (
	Temp_Maddsub__n0000__n0049(0)/Temp_Maddsub__n0000__n0049(0)_D2 AND